casper-astro / hdl_devel

Related projects: ⓘ

• udara28 / SDRAM_Controller
  Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)
  ☆20Updated 8 years ago
• andrecp / myhdl_simple_uart
  A very simple UART implementation in MyHDL
  ☆17Updated 10 years ago
• quartiq / redpid
  migen + misoc + redpitaya = digital servo
  ☆34Updated 5 years ago
• hgomersall / Veriutils
  Verification Utilities for MyHDL
  ☆17Updated 10 months ago
• AnttiLukats / HackaZynq
  Open Source ZYNQ Board
  ☆30Updated 9 years ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆33Updated 3 years ago
• ipbus / ipbus-software
  Software that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol
  ☆22Updated last month
• RISCV-on-Microsemi-FPGA / SoftConsole
  Eclipse based IDE for RISC-V bare metal software development.
  ☆19Updated 4 years ago
• ipbus / ipbus-firmware
  Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol
  ☆40Updated last week
• drom / logidrom
  Digital Circuit rendering engine
  ☆31Updated last year
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆39Updated 3 months ago
• jck / uhdl
  Utilities for MyHDL
  ☆17Updated 9 months ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆33Updated 7 years ago
• enjoy-digital / arty-soc
  ☆11Updated this week
• Gordonei / MyHDL-based-FPGA-DSP-Toolflow
  A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. T…
  ☆24Updated 12 years ago
• binary-logic / vj-uart
  Virtual JTAG UART for Altera Devices
  ☆45Updated 10 years ago
• swetland / zynq-sandbox
  a playground for xilinx zynq fpga experiments
  ☆48Updated 5 years ago
• devbisme / myhdlpeek
  Monitor and display signal waveforms from your MyHDL/nMigen digital design in a Jupyter notebook.
  ☆39Updated 7 months ago
• hamsternz / FPGA_GigabitTx
  Sending UDP packets out over a Gigabit PHY with an FPGA.
  ☆42Updated 8 years ago
• cyrozap / python-bsdl-parser
  A Grako-based parser for IEEE 1149.1 Boundary-Scan Description Language (BSDL) files
  ☆24Updated 3 years ago
• BerkeleyLab / Marble-Mini
  "Marble-Mini" Simple FMC carrier board with SFP, 2x FMC, PoE
  ☆16Updated 2 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 2 years ago
• witchard / nbwavedrom
  A simple function to add wavedrom diagrams into an ipython notebook.
  ☆22Updated 2 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆20Updated 5 years ago
• alvieboy / ZPUino-HDL
  ZPUino HDL implementation
  ☆88Updated 6 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• PyLCARS / PythonUberHDL
  Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL
  ☆34Updated 5 years ago
• wware / myblaze
  MyBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in MyHDL (http://www.myhdl.org). It started as a translation of…
  ☆17Updated 11 years ago
• carlos-jenkins / csv2vcd
  Signal analyzer CSV to IEEE 1364-2001 VCD file format converter.
  ☆11Updated 3 years ago
• FMCHUB / Lib_Altium
  Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
  ☆42Updated 2 years ago