yanidubin / parallella-fpga-tutorials

Related projects ⓘ

Alternatives and complementary repositories for parallella-fpga-tutorials

• daveshah1 / ElasticC
  lightweight open HLS for FPGA rapid prototyping
  ☆20Updated 6 years ago
• Kirill888 / parallella-fpga-dummy-io
  Sample minimal Vivado project for Parallella FPGA
  ☆43Updated 8 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• olofk / i2c
  I2C controller core
  ☆16Updated 2 years ago
• alvieboy / ZPUino-HDL
  ZPUino HDL implementation
  ☆89Updated 6 years ago
• lzw545 / opengg
  OpenGL-like graphics pipeline on a Xilinx FPGA
  ☆30Updated 13 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆20Updated 5 years ago
• cambridgehackers / fpgajtag
  A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.
  ☆34Updated 2 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• devbisme / CAT-Board
  The CAT Board is a Raspberry Pi HAT with a Lattice iCE40HX FPGA.
  ☆60Updated 8 months ago
• parallella / parallella-fpga
  FPGA Development for the parallella
  ☆19Updated 7 years ago
• fusesoc / sd_device
  SD device emulator from ProjectVault
  ☆14Updated 5 years ago
• FPGAwars / toolchain-icestorm
  Icestorm, Arachne-pnr and Yosys pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS
  ☆38Updated 2 years ago
• cyrozap / openocd-xilinx-loader
  Some Python scripts to program Xilinx FPGAs using OpenOCD
  ☆24Updated 8 years ago
• olofk / simple_spi
  SPI core
  ☆15Updated 5 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 6 years ago
• myriadrf / STREAM
  FPGA development platform for high-performance RF and digital design
  ☆31Updated 8 years ago
• knielsen / ice40_viewer
  ☆58Updated last year
• peteasa / parallella-yoctobuild
  A Simple to use build environment for parallella using yocto
  ☆13Updated 5 years ago
• m-labs / microscope
  Finding the bacteria in rotting FPGA designs.
  ☆13Updated 3 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated last year
• Galland / LEON2
  LEON2 SPARC CPU IP core LGPL by Gaisler Research
  ☆18Updated 11 years ago
• warclab / dyract
  DyRACT Open Source Repository
  ☆16Updated 8 years ago
• daveshah1 / flow-examples
  Misc open FPGA flow examples
  ☆8Updated 4 years ago
• ArcaneNibble / project-chibi
  Altera MAX V bitstream documentation -- CLEANUP PENDING
  ☆19Updated 4 years ago
• embecosm / chiphack
  Repository and Wiki for Chip Hack events.
  ☆50Updated 3 years ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆79Updated 3 years ago