dawsonjon / Chips-DemoLinks
Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.
☆16Updated 7 years ago
Alternatives and similar repositories for Chips-Demo
Users that are interested in Chips-Demo are comparing it to the libraries listed below
Sorting:
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆67Updated 3 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆19Updated 5 years ago
- HW and SW based implementation of Canny Edge Detection Algorithm.☆12Updated 7 years ago
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆89Updated 7 years ago
- IP operations in verilog (simulation and implementation on ice40)☆61Updated 6 years ago
- wifi☆12Updated 8 years ago
- A collection of phase locked loop (PLL) related projects☆111Updated last year
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆58Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- FIR implemention with Verilog☆49Updated 6 years ago
- Digital Interpolation Techniques Applied to Digital Signal Processing☆65Updated last year
- spi memory controller☆22Updated 8 years ago
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 5 years ago
- Ethernet 10GE MAC☆46Updated 11 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 13 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆75Updated last year
- RTL Verilog library for various DSP modules☆91Updated 3 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆32Updated 5 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- ☆19Updated 4 years ago
- FPGA纯逻辑实现modbus通信☆22Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- Partial Verilog implimentation of a WiMAX OFDM Phy☆19Updated 13 years ago
- Hardware implementation of HDR image producing algorithm☆16Updated 3 years ago
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆28Updated 4 years ago
- Verilog based BCH encoder/decoder☆125Updated 3 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago