dawsonjon / Chips-Demo
Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.
☆14Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for Chips-Demo
- Fork of OpenCores jpegencode with Cocotb testbench☆42Updated 9 years ago
- spi memory controller☆21Updated 7 years ago
- Extensible FPGA control platform☆53Updated last year
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago
- JESD204b modules in VHDL☆29Updated 5 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆26Updated 3 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆41Updated 2 years ago
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆12Updated 6 years ago
- Digital Interpolation Techniques Applied to Digital Signal Processing☆54Updated 4 months ago
- development interface mil-std-1553b for system on chip☆19Updated 6 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆30Updated last month
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- AXI Stream UART (verilog)☆9Updated 5 years ago
- Open FPGA Modules☆22Updated last month
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆88Updated 6 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆39Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆78Updated 5 years ago
- SDRAM controller for MIPSfpga+ system☆20Updated 4 years ago
- IP Cores that can be used within Vivado☆24Updated 3 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Wishbone to AXI bridge (VHDL)☆37Updated 5 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆22Updated 6 years ago
- WISHBONE DMA/Bridge IP Core☆17Updated 10 years ago
- SPI-Flash XIP Interface (Verilog)☆35Updated 3 years ago
- A collection of phase locked loop (PLL) related projects☆99Updated 9 months ago
- Fixed-point math library with VHDL, Python and MATLAB support☆18Updated 3 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆29Updated 4 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- UART -> AXI Bridge☆55Updated 3 years ago