Alternatives and similar repositories for Chips-Demo

Users that are interested in Chips-Demo are comparing it to the libraries listed below

• drom / spi
  spi memory controller
  ☆22Updated 8 years ago
• analogdevicesinc / fpgahdl_xilinx
  (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…
  ☆89Updated 7 years ago
• vitaliikulin / I2C-FPGA-Verilog-HDL
  In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…
  ☆20Updated 5 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆67Updated 2 weeks ago
• tchoyt / pynq_dev
  Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development
  ☆12Updated 7 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆113Updated last year
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• jsyk / miilink
  Connecting FPGA and MCU using Ethernet RMII
  ☆23Updated 9 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆46Updated 10 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆35Updated 4 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆61Updated 6 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆86Updated 2 years ago
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 13 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆59Updated 3 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆39Updated 4 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• hukenovs / fp23fftk
  Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
  ☆61Updated 3 years ago
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆23Updated 7 years ago
• txzing / modbus_crc_verilog
  FPGA纯逻辑实现modbus通信
  ☆22Updated 3 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆35Updated 8 months ago
• m-labs / tdc-core
  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
  ☆65Updated 10 years ago
• xupsh / Digital-Design-Reference-Design
  ☆24Updated 9 years ago
• markos-stefanidis / FPGA-Based-HDR-algorithm
  Hardware implementation of HDR image producing algorithm
  ☆16Updated 3 years ago
• freecores / ha1588
  Hardware Assisted IEEE 1588 IP Core
  ☆29Updated 11 years ago
• jchengX / MAC_BFM
  wifi
  ☆12Updated 8 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆43Updated 6 years ago
• ZipCPU / interpolation
  Digital Interpolation Techniques Applied to Digital Signal Processing
  ☆66Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago