paulscherrerinstitute / psi_fpga_all
Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
☆33Updated 10 months ago
Alternatives and similar repositories for psi_fpga_all:
Users that are interested in psi_fpga_all are comparing it to the libraries listed below
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- UART -> AXI Bridge☆60Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- ☆32Updated last year
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 3 weeks ago
- USB 2.0 Device IP Core☆59Updated 7 years ago
- Repository gathering basic modules for CDC purpose☆51Updated 5 years ago
- Verilog SPI master and slave☆50Updated 9 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆65Updated 2 years ago
- An open-source HDL register code generator fast enough to run in real time.☆44Updated this week
- UART models for cocotb☆26Updated last year
- Verilog digital signal processing components☆126Updated 2 years ago
- RTL Verilog library for various DSP modules☆84Updated 3 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆65Updated 2 years ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆31Updated 3 years ago
- ☆58Updated 3 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆22Updated 2 years ago
- I2C models for cocotb☆29Updated 10 months ago
- IEEE P1735 decryptor for VHDL☆29Updated 9 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆143Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆62Updated 4 years ago
- Ethernet interface modules for Cocotb☆59Updated last year
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆13Updated 2 years ago
- Control and Status Register map generator for HDL projects☆109Updated this week
- Extensible FPGA control platform☆57Updated last year
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆93Updated 4 years ago
- JESD204b modules in VHDL☆29Updated 5 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆65Updated 2 weeks ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 10 years ago
- Slides and lab instructions for the mastering MicroBlaze session☆34Updated 2 years ago