Alternatives and similar repositories for psi_fpga_all

Users that are interested in psi_fpga_all are comparing it to the libraries listed below

• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆53Updated 2 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆81Updated last month
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆69Updated 4 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆128Updated 7 months ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆39Updated 10 months ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆160Updated 10 months ago
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆38Updated 4 months ago
• hypernyan / eth_vlg
  ☆77Updated 3 years ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆26Updated last year
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆81Updated 3 years ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆60Updated 2 months ago
• ATaylorCEngFIET / Mastering-MicroBlaze
  Slides and lab instructions for the mastering MicroBlaze session
  ☆36Updated 3 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆32Updated 4 months ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆57Updated 6 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆95Updated 3 years ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 11 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆64Updated 4 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆78Updated 3 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 3 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆97Updated 5 years ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆73Updated this week
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆115Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆168Updated 3 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 5 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆194Updated last month
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆123Updated 2 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆36Updated last month