Alternatives and similar repositories for psi_fpga_all

Users that are interested in psi_fpga_all are comparing it to the libraries listed below

• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆61Updated 3 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated 3 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆71Updated 2 years ago
• hypernyan / eth_vlg
  ☆70Updated 3 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 5 years ago
• ATaylorCEngFIET / Mastering-MicroBlaze
  Slides and lab instructions for the mastering MicroBlaze session
  ☆35Updated 2 years ago
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆35Updated 2 months ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆55Updated 4 years ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆32Updated 9 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆82Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆52Updated last year
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆68Updated this week
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆88Updated 3 years ago
• kkudrolli / USB-Host
  Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …
  ☆14Updated 10 years ago
• schang412 / cocotbext-spi
  ☆21Updated last month
• gtjennings1 / JPEG_Encoder
  ☆15Updated 6 years ago
• mbuesch / crcgen
  Generator for CRC HDL code (VHDL, Verilog, MyHDL)
  ☆37Updated last year
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆63Updated 2 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆116Updated last week
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆15Updated 10 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 4 months ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆65Updated last year
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆65Updated 7 months ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆40Updated 7 years ago
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆45Updated 9 years ago