Alternatives and similar repositories for FPGA-Guide

Users that are interested in FPGA-Guide are comparing it to the libraries listed below

• ZipCPU / qoiimg
  Quite OK image compression Verilog implementation
  ☆23Updated last year
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆54Updated 2 years ago
• ecilasun / NekoIchi
  A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
  ☆31Updated 4 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆108Updated 2 weeks ago
• dpretet / friscv
  RISCV CPU implementation in SystemVerilog
  ☆32Updated last month
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆90Updated 11 months ago
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆18Updated 7 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆62Updated last year
• sifferman / fusesoc_template
  Example of how to get started with olofk/fusesoc.
  ☆18Updated 4 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆28Updated 4 years ago
• wtiandong / Hardware_circular_buffer_controller
  This is a circular buffer controller used in FPGA.
  ☆34Updated 9 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆48Updated 5 months ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆72Updated 3 weeks ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆35Updated this week
• kiwih / qtcore-C1
  ☆47Updated 2 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆25Updated 3 years ago
• aignacio / nox
  RISC-V Nox core
  ☆69Updated 4 months ago
• aignacio / mpsoc_example
  ☆60Updated 4 years ago
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆41Updated 2 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆48Updated last week
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 4 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆39Updated last week
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆33Updated 2 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆20Updated 3 weeks ago
• AEW2015 / fpga-colab
  FPGA examples on Google Colab
  ☆27Updated 3 months ago
• riadhbenabdelhamid / BRISKI
  BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …
  ☆28Updated 2 months ago
• phoeniX-Digital-Design / phoeniX
  A Reconfigurable RISC-V Core for Approximate Computing
  ☆127Updated 6 months ago
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆34Updated 4 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 4 months ago
• EECS150 / asic-labs-fa22
  ☆20Updated 2 years ago