Alternatives and similar repositories for intfftk

Users that are interested in intfftk are comparing it to the libraries listed below

• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆115Updated 4 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆107Updated last year
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆46Updated 4 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• FMCHUB / Lib_Altium
  Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
  ☆43Updated 3 years ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆69Updated 7 years ago
• ZipCPU / interpolation
  Digital Interpolation Techniques Applied to Digital Signal Processing
  ☆62Updated last year
• ZipCPU / dblclockfft
  A configurable C++ generator of pipelined Verilog FFT cores
  ☆242Updated last year
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 4 years ago
• ZipCPU / dspfilters
  A collection of demonstration digital filters
  ☆154Updated last year
• hukenovs / fp23fftk
  Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
  ☆60Updated 3 years ago
• mattvenn / fpga-sdft
  sliding DFT for FPGA, targetting Lattice ICE40 1k
  ☆77Updated 5 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆110Updated 8 months ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆46Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 7 years ago
• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆80Updated 4 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆62Updated this week
• yrrapt / amsat_txrx_ic
  An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
  ☆72Updated 3 years ago
• dawsonjon / FPGA-radio
  Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
  ☆108Updated 8 years ago
• MorrisMA / 1PPS-DPLL
  DPLL for phase-locking to 1PPS signal
  ☆32Updated 8 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆143Updated 2 years ago
• strath-sdr / rfsoc_sam
  RFSoC Spectrum Analyser Module on PYNQ.
  ☆82Updated last year
• chili-chips-ba / openeye-CamSI
  A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …
  ☆51Updated 3 weeks ago
• ZipCPU / sdr
  A basic Soft(Gate)ware Defined Radio architecture
  ☆88Updated last year
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆45Updated last month
• davemuscle / sigma_delta_converters
  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
  ☆69Updated 3 years ago
• 0xArt / Tiny_But_Mighty_I2C_Master_Verilog
  I2C Master Verilog module
  ☆34Updated last month
• ldoolitt / vhd2vl
  ☆134Updated 7 months ago