Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
☆87Jan 31, 2023Updated 3 years ago
Alternatives and similar repositories for intfftk
Users that are interested in intfftk are comparing it to the libraries listed below
Sorting:
- Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).☆62Jul 5, 2022Updated 3 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆128Feb 11, 2021Updated 5 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 5 years ago
- A configurable C++ generator of pipelined Verilog FFT cores☆255Apr 18, 2024Updated last year
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- VHDL Library for implementing common DSP functionality.☆31Oct 5, 2018Updated 7 years ago
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 5 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Mar 22, 2018Updated 7 years ago
- The source code for the XTRX FPGA image☆17Nov 19, 2022Updated 3 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Vector Network Analyzer 10 KHz - 180 MHz☆25Sep 2, 2018Updated 7 years ago
- RFNoC out-of-tree module for a channelizer☆16Mar 14, 2018Updated 7 years ago
- Synthesizable FIR filters in VHDL☆14Jul 19, 2019Updated 6 years ago
- Collection of hardware description languages writings and code snippets☆28Jan 29, 2015Updated 11 years ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 6 years ago
- synthesizable FFT IP block for FPGA designs☆32Apr 16, 2019Updated 6 years ago
- A wishbone controlled FM transmitter hack☆24Jan 16, 2024Updated 2 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 10 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆44Jan 18, 2024Updated 2 years ago
- JESD204B core for Migen/MiSoC☆35May 5, 2021Updated 4 years ago
- Verilog for the Bus Pirate Ultra FPGA☆26Dec 12, 2019Updated 6 years ago
- Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.☆39Oct 5, 2020Updated 5 years ago
- ☆10Oct 18, 2024Updated last year
- SPI ELF bootloader for Xilinx Microblaze processors☆27Oct 17, 2017Updated 8 years ago
- Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)☆31Aug 14, 2020Updated 5 years ago
- Implementation of FM (frequency modulation) radio transmitter in FPGA Altera Cyclone III.☆14May 16, 2016Updated 9 years ago
- Realtime audio DSP on the ZyBo☆10Jan 25, 2016Updated 10 years ago
- Griffinfly is COSIC's submission to the ZPRIZE competition under the category, Accelerating NTT Operations on an FPGA by Michiel Van Beir…☆11Feb 13, 2023Updated 3 years ago
- an sata controller using smallest resource.☆17Feb 5, 2014Updated 12 years ago
- A vhdl package for reading and writing bitmap files.☆11Jan 9, 2018Updated 8 years ago
- SDR-Transceiver☆10Dec 30, 2019Updated 6 years ago
- FPGArduino binary☆13Aug 5, 2019Updated 6 years ago
- Hardware and support board schematics☆17Nov 10, 2016Updated 9 years ago
- USB1.1 Host Controller + PHY☆15Aug 4, 2021Updated 4 years ago
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆11Dec 20, 2013Updated 12 years ago
- FPGA-based I2C to RS-232 serial converter / bus monitor☆13Jan 29, 2016Updated 10 years ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 11 years ago