Computing in memory optimizes data handling by performing operations directly in memory, ideal for high-speed data processing needs. This compilation highlights its technologies and applications, offering a concise overview for professionals in the field.
☆36Nov 22, 2024Updated last year
Alternatives and similar repositories for CIM-Technical-Papers-Collection
Users that are interested in CIM-Technical-Papers-Collection are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆144Oct 29, 2025Updated 8 months ago
- Official code of paper "MICSim: A Modular Simulator for Mixed-signal Compute-in-Memory based AI Accelerator", ASP-DAC 2025☆39Oct 15, 2025Updated 9 months ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆32Nov 2, 2023Updated 2 years ago
- ☆22Jan 16, 2026Updated 6 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆47May 25, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆105Jul 9, 2026Updated last week
- a Computing In Memory emULATOR framework☆16May 19, 2024Updated 2 years ago
- Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"☆60Sep 1, 2025Updated 10 months ago
- ☆158Jun 24, 2024Updated 2 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆113Apr 26, 2025Updated last year
- for paper @ ASPLOS‘25’☆16Mar 27, 2025Updated last year
- ☆77Feb 12, 2025Updated last year
- Central repository for all NeuroSim versions. Each version is uploaded in a separate branch. Updates to the versions will be reflected he…☆133Updated this week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- ☆30Feb 27, 2025Updated last year
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆14Mar 3, 2023Updated 3 years ago
- NVSim - A performance, energy and area estimation tool for non-volatile memory (NVM)☆142Aug 27, 2018Updated 7 years ago
- Source code for the architectural simulator used for modeling the PUD system proposed in our HPCA 2024 paper `MIMDRAM: An End-to-End Proc…☆30Sep 12, 2025Updated 10 months ago
- Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025☆142May 3, 2025Updated last year
- [Nature Communications 2023] "Wearable in-sensor reservoir computing using optoelectronic polymers with through-space charge-transport ch…☆17Jan 11, 2023Updated 3 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆23Oct 9, 2020Updated 5 years ago
- ☆12Aug 18, 2023Updated 2 years ago
- ☆21Mar 9, 2026Updated 4 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CrossSim: accuracy simulation of analog in-memory computing☆213Jun 3, 2026Updated last month
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆37May 19, 2022Updated 4 years ago
- ☆17Jul 31, 2024Updated last year
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆136Aug 27, 2024Updated last year
- ☆18Jan 10, 2026Updated 6 months ago
- ☆19Jan 13, 2026Updated 6 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆53Jun 1, 2021Updated 5 years ago
- RPCNIC: A High-Performance and Reconfigurable PCIe-attached RPC Accelerator [HPCA2025]☆15Dec 9, 2024Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆40Nov 24, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Modeling of memristors in LTSpise environment☆47Dec 9, 2025Updated 7 months ago
- Hardware Division Units☆10Jul 17, 2014Updated 12 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆19Jul 9, 2024Updated 2 years ago
- Verilog and Python drivers and APIs for Neurram 48-core chip☆45May 17, 2022Updated 4 years ago
- A Framework for Hardware-Aware LLM Exploration☆39Updated this week
- Dysl-vla:Official code for "DySL-VLA: Efficient Vision-Language-Action Model Inference via Dynamic-Static Layer-Skipping for Robot Manipu…☆25Jul 9, 2026Updated last week
- A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley☆14Nov 30, 2020Updated 5 years ago