Alternatives and similar repositories for yavhdl

Users that are interested in yavhdl are comparing it to the libraries listed below

• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆75Updated 6 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 7 months ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆80Updated 4 years ago
• knielsen / ice40_viewer
  ☆61Updated last year
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆70Updated 3 years ago
• whitequark / Yumewatari
  妖刀夢渡
  ☆59Updated 6 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• daveshah1 / ElasticC
  lightweight open HLS for FPGA rapid prototyping
  ☆20Updated 7 years ago
• forflo / yodl
  A VHDL frontend for Yosys
  ☆103Updated 8 years ago
• ArcaneNibble / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 7 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 4 months ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆46Updated 6 months ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• emard / ulx3s-misc
  Miscellaneous ULX3S examples (advanced)
  ☆78Updated 2 months ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆66Updated last month
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆44Updated 3 months ago
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆114Updated 3 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 7 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 6 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆85Updated 5 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 10 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆53Updated 3 months ago
• olofk / vidbo
  Virtual Development Board
  ☆60Updated 3 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆98Updated 2 years ago