FlightLLM / flightllm_test_demoLinks
☆27Updated last year
Alternatives and similar repositories for flightllm_test_demo
Users that are interested in flightllm_test_demo are comparing it to the libraries listed below
Sorting:
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆83Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆151Updated this week
- A DSL for Systolic Arrays☆81Updated 6 years ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆124Updated last year
- ☆71Updated 5 years ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- Machine-Learning Accelerator System Exploration Tools☆173Updated 2 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆146Updated 6 months ago
- An HLS based winograd systolic CNN accelerator☆53Updated 4 years ago
- ACM TODAES Best Paper Award, 2022☆26Updated last year
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆46Updated 9 months ago
- ☆72Updated 2 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆137Updated 2 months ago
- ☆35Updated 5 years ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- ☆37Updated 5 months ago
- An FPGA Accelerator for Transformer Inference☆88Updated 3 years ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆53Updated last year
- FRAME: Fast Roofline Analytical Modeling and Estimation☆37Updated last year
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆27Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 6 months ago
- PyTorch model to RTL flow for low latency inference☆131Updated last year
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆198Updated 5 years ago
- NeuraLUT-Assemble☆38Updated last week
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆62Updated 5 months ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆67Updated 5 years ago