FlightLLM / flightllm_test_demo
☆20Updated last year
Alternatives and similar repositories for flightllm_test_demo:
Users that are interested in flightllm_test_demo are comparing it to the libraries listed below
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆85Updated 4 months ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆103Updated 9 months ago
- ☆83Updated last year
- Allo: A Programming Model for Composable Accelerator Design☆192Updated this week
- RTL implementation of Flex-DPE.☆97Updated 5 years ago
- ☆69Updated 4 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆77Updated 7 months ago
- Eyeriss chip simulator☆36Updated 4 years ago
- ☆38Updated last year
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆93Updated 2 weeks ago
- Release of stream-specialization software/hardware stack.☆120Updated last year
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆121Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆61Updated 3 years ago
- IC implementation of TPU☆99Updated 5 years ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆164Updated this week
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆46Updated this week
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆46Updated 2 weeks ago
- Machine-Learning Accelerator System Exploration Tools☆147Updated this week
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆33Updated last month
- ☆43Updated 3 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆36Updated 2 years ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆71Updated 2 years ago
- PyTorch model to RTL flow for low latency inference☆125Updated 11 months ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆55Updated 3 years ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆106Updated last year
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆103Updated last year
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆180Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago