Xilinx / RFSoC-PYNQLinks
Python productivity for RFSoC platforms
☆72Updated last year
Alternatives and similar repositories for RFSoC-PYNQ
Users that are interested in RFSoC-PYNQ are comparing it to the libraries listed below
Sorting:
- PYNQ example of using the RFSoC as a QPSK transceiver.☆103Updated 2 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆32Updated 2 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆49Updated 2 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆24Updated last year
- An RFSoC Frequency Planner developed using Python.☆28Updated 2 years ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆62Updated 4 years ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆37Updated 2 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆19Updated 6 months ago
- Board repo for the ZCU216 RFSOC☆28Updated 2 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆79Updated 11 months ago
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆39Updated 2 years ago
- A collection of RFSoC introductory notebooks for PYNQ.☆23Updated 3 years ago
- Companion Jupyter Notebooks for the RFSoC-Book.☆184Updated 2 years ago
- ☆19Updated 3 years ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 2 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆61Updated 3 years ago
- Repository for FPGA projects☆51Updated 7 months ago
- 10G Low Latency Ethernet☆54Updated last year
- Demonstration of Automatic Gain Control with PYNQ☆14Updated 2 years ago
- FPGA and Digital ASIC Build System☆74Updated 2 weeks ago
- Board files to build the ZCU111 PYNQ image☆19Updated 2 years ago
- ☆27Updated 3 years ago
- Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.☆66Updated 3 months ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- JESD204b modules in VHDL☆30Updated 6 years ago
- An HDL design for sending data over Ethernet☆43Updated 2 years ago
- A collection of phase locked loop (PLL) related projects☆106Updated last year
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆59Updated 3 years ago