Alternatives and similar repositories for rfsoc_qpsk

Users that are interested in rfsoc_qpsk are comparing it to the libraries listed below

• strath-sdr / rfsoc_sam
  RFSoC Spectrum Analyser Module on PYNQ.
  ☆82Updated last year
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• Xilinx / RFSoC-PYNQ
  Python productivity for RFSoC platforms
  ☆78Updated 3 weeks ago
• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆50Updated 2 years ago
• dshekhalev / FEC
  FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
  ☆109Updated last year
• Xilinx / PYNQ_RFSOC_Workshop
  Open-sourcing the PYNQ & RFSoC workshop materials
  ☆62Updated 4 years ago
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆29Updated 2 years ago
• strath-sdr / rfsoc_qsfp_offload
  RFSoC QSFP Data Offload Design with GNU Radio
  ☆22Updated 7 months ago
• strath-sdr / rfsoc_studio
  The Strathclyde RFSoC Studio Installer for PYNQ.
  ☆32Updated 2 years ago
• strath-sdr / rfsoc_radio
  PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.
  ☆37Updated 2 years ago
• strath-sdr / RFSoC-Book
  Companion Jupyter Notebooks for the RFSoC-Book.
  ☆194Updated 2 years ago
• strath-sdr / rfsoc_notebooks
  A collection of RFSoC introductory notebooks for PYNQ.
  ☆23Updated 3 years ago
• sarafs1926 / ZCU216-PYNQ
  Board repo for the ZCU216 RFSOC
  ☆29Updated 3 years ago
• Xilinx / DSP-PYNQ
  A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
  ☆39Updated 3 years ago
• OpenResearchInstitute / dvb_fpga
  RTL implementation of components for DVB-S2
  ☆121Updated 2 years ago
• Xilinx / SDFEC-PYNQ
  A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC
  ☆13Updated 3 years ago
• jfoshea / Viterbi-Decoder-in-Verilog
  An efficient implementation of the Viterbi decoding algorithm in Verilog
  ☆54Updated last year
• Xilinx / RFSoC-MTS
  A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).
  ☆24Updated 2 years ago
• JennySmith888 / 100GBE-PYNQ
  ☆19Updated 3 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆107Updated last year
• mathworks / HDL-Coder-Self-Guided-Tutorial
  Learn how to deploy an algorithm to an FPGA using MATLAB and Simulink.
  ☆78Updated 6 months ago
• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆71Updated 2 years ago
• strath-sdr / pynq_agc
  Demonstration of Automatic Gain Control with PYNQ
  ☆15Updated 3 years ago
• EttusResearch / fpga
  The USRP™ Hardware Driver FPGA Repository
  ☆291Updated 3 years ago
• Teddy-van-Jerry / sdr-psk-fpga
  Dual-Mode PSK Transceiver on SDR With FPGA
  ☆38Updated 9 months ago
• Grootzz / AD9361_TX_MSK
  A project demonstrate how to config ad9361 to TX mode and how to transmit MSK
  ☆58Updated 6 years ago
• analogdevicesinc / TransceiverToolbox
  MATLAB toolbox for ADI transceiver products
  ☆62Updated 3 months ago
• yugithub / OFDM-baseband
  Verilog实现OFDM基带
  ☆44Updated 9 years ago
• catkira / open5G_phy
  A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
  ☆209Updated 2 months ago
• Xilinx / Vitis_Model_Composer
  Vitis Model Composer Examples and Tutorials
  ☆102Updated 3 weeks ago