Alternatives and similar repositories for soc-prebuilt-firmware

Users that are interested in soc-prebuilt-firmware are comparing it to the libraries listed below

• Xilinx / meta-xilinx-tools
  Yocto Project layer enables AMD Xilinx tools related metadata for MicroBlaze, Zynq, ZynqMP and Versal devices.
  ☆61Updated last week
• Xilinx / gen-machine-conf
  Parse hardware design information to generate project specific machine configuration
  ☆12Updated last week
• k0nze / qemu_zynq_linux_setup
  Tutorial on installing QEMU to simulate Zynq Devices with Petalinux
  ☆22Updated 8 years ago
• arm-university / Modern-System-on-Chip-Design-on-Arm
  A textbook on system on chip design using Arm Cortex-A
  ☆32Updated last year
• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆59Updated 2 months ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated 2 weeks ago
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆26Updated 5 years ago
• antmicro / zynq-mkbootimage
  An open source replacement of the Xilinx bootgen application.
  ☆106Updated last year
• arm-university / System-on-Chip-Design-with-Arm-Cortex-M-Processors
  A reference book on System-on-Chip Design
  ☆29Updated last year
• Xilinx / meta-xilinx
  Collection of Yocto Project layers to enable AMD Xilinx products
  ☆160Updated last week
• Xilinx / XilinxCEDStore
  This store contains Configurable Example Designs.
  ☆46Updated 2 weeks ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆93Updated this week
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆67Updated 2 weeks ago
• ATaylorCEngFIET / Vitis_Hero
  ☆27Updated 3 years ago
• Xilinx / bootgen
  bootgen source code
  ☆45Updated last week
• Digilent / digilent-vivado-scripts
  ☆69Updated 2 months ago
• RealDigitalOrg / RFSoC4x2-BSP
  ☆15Updated 5 months ago
• intel / fpga-partial-reconfig
  Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  ☆88Updated 3 months ago
• Xilinx / Embedded-Design-Tutorials
  ☆136Updated last month
• Xilinx / system-device-tree-xlnx
  ☆16Updated 2 weeks ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated 3 weeks ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 5 months ago
• Xilinx-Wiki-Projects / ZCU102-Ethernet
  Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.
  ☆66Updated 3 months ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆53Updated this week
• fabriziotappero / opencores-scraper
  few python scripts to clone all IP cores from opencores.org
  ☆22Updated last year
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆121Updated 3 weeks ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆28Updated 4 years ago
• ATaylorCEngFIET / Xilinx_BootCamp
  Slides and material for Xilinx bootcamp
  ☆22Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last year