Xilinx / soc-prebuilt-firmware
☆12Updated 4 months ago
Alternatives and similar repositories for soc-prebuilt-firmware:
Users that are interested in soc-prebuilt-firmware are comparing it to the libraries listed below
- Yocto Project layer enables AMD Xilinx tools related metadata for MicroBlaze, Zynq, ZynqMP and Versal devices.☆59Updated 3 weeks ago
- Tutorial on installing QEMU to simulate Zynq Devices with Petalinux☆21Updated 7 years ago
- The multi-core cluster of a PULP system.☆89Updated 3 weeks ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- ☆25Updated 2 years ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 5 months ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆59Updated last month
- ☆130Updated this week
- FPGA and Digital ASIC Build System☆74Updated this week
- ☆15Updated 4 months ago
- Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.☆63Updated 2 months ago
- A reference book on System-on-Chip Design☆25Updated last year
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆92Updated last year
- Repo Manifests for the Yocto Project Build System☆32Updated 3 months ago
- ☆131Updated last year
- ☆31Updated this week
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆95Updated 2 weeks ago
- A textbook on understanding system on chip design☆34Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- ☆53Updated 2 years ago
- HW Design Collateral for Caliptra RoT IP☆89Updated this week
- Slides and material for Xilinx bootcamp☆21Updated 3 years ago
- This is forked from Xilinx HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL☆26Updated 3 years ago
- ☆15Updated 4 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆96Updated last month
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆54Updated 3 months ago
- ☆69Updated last month