strath-sdr / pynq_agcLinks
Demonstration of Automatic Gain Control with PYNQ
☆15Updated 3 years ago
Alternatives and similar repositories for pynq_agc
Users that are interested in pynq_agc are comparing it to the libraries listed below
Sorting:
- An RFSoC Frequency Planner developed using Python.☆30Updated 2 years ago
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆105Updated 2 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆23Updated 9 months ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆32Updated 2 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆50Updated 2 years ago
- Python productivity for RFSoC platforms☆79Updated 2 months ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆37Updated 2 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆84Updated last year
- A collection of RFSoC introductory notebooks for PYNQ.☆23Updated 3 years ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 3 years ago
- Board repo for the ZCU216 RFSOC☆29Updated 3 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆26Updated 2 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆116Updated last year
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆39Updated 3 years ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆62Updated 4 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- Vitis Model Composer Examples and Tutorials☆105Updated last week
- Digital Signal Processing and Well-Known Modulations on HDL☆41Updated 3 months ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆76Updated 2 years ago
- ☆19Updated 3 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- MATLAB toolbox for ADI transceiver products☆63Updated 5 months ago
- A collection of phase locked loop (PLL) related projects☆108Updated last year
- Learn how to deploy an algorithm to an FPGA using MATLAB and Simulink.☆83Updated 7 months ago
- RTL implementation of components for DVB-S2☆122Updated 2 years ago
- IEEE 802.11 OFDM-based transceiver system☆35Updated 7 years ago
- Companion Jupyter Notebooks for the RFSoC-Book.☆224Updated 2 years ago
- A basic Soft(Gate)ware Defined Radio architecture☆93Updated last year
- HDL code for a complex multiplier with AXI stream interface☆16Updated 2 years ago