strath-sdr / RFSoC-Book
Companion Jupyter Notebooks for the RFSoC-Book.
☆147Updated last year
Related projects ⓘ
Alternatives and complementary repositories for RFSoC-Book
- PYNQ example of using the RFSoC as a QPSK transceiver.☆91Updated last year
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆44Updated last year
- RFSoC Spectrum Analyser Module on PYNQ.☆69Updated 4 months ago
- Python productivity for RFSoC platforms☆57Updated 6 months ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆56Updated 4 years ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆31Updated last year
- The Strathclyde RFSoC Studio Installer for PYNQ.☆26Updated last year
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- An RFSoC Frequency Planner developed using Python.☆20Updated last year
- A collection of RFSoC introductory notebooks for PYNQ.☆19Updated 3 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆15Updated 5 months ago
- A collection of demonstration digital filters☆140Updated 10 months ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆87Updated 5 months ago
- Board repo for the ZCU216 RFSOC☆25Updated 2 years ago
- Demonstration of Automatic Gain Control with PYNQ☆11Updated 2 years ago
- This repository includes the source codes for the mmWave SDR developed at the University of South Carolina for the AERPAW at NCSU for wir…☆41Updated 2 months ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆21Updated last month
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆37Updated 2 years ago
- A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC☆24Updated 2 months ago
- Repository for FPGA projects☆43Updated last month
- A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog☆193Updated last year
- Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC☆84Updated 8 years ago
- Learn how to deploy an algorithm to an FPGA using MATLAB and Simulink.☆62Updated 5 months ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆45Updated 8 months ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆52Updated 5 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆50Updated 3 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆20Updated last year
- MATLAB toolbox for ADI transceiver products☆57Updated this week
- A collection of phase locked loop (PLL) related projects☆99Updated 10 months ago
- Verilog digital signal processing components☆107Updated 2 years ago