Xilinx / RFSoC2x2-PYNQ
RFSoC2x2 board repo for PYNQ
☆17Updated 2 years ago
Alternatives and similar repositories for RFSoC2x2-PYNQ:
Users that are interested in RFSoC2x2-PYNQ are comparing it to the libraries listed below
- An RFSoC Frequency Planner developed using Python.☆20Updated last year
- A collection of RFSoC introductory notebooks for PYNQ.☆19Updated 3 years ago
- Demonstration of Automatic Gain Control with PYNQ☆12Updated 2 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆94Updated last year
- RFSoC QSFP Data Offload Design with GNU Radio☆17Updated last month
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆44Updated last year
- ☆18Updated 3 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆27Updated last year
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 2 years ago
- Board repo for the ZCU216 RFSOC☆25Updated 2 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆70Updated 6 months ago
- Python productivity for RFSoC platforms☆61Updated 7 months ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆32Updated last year
- Open-sourcing the PYNQ & RFSoC workshop materials☆56Updated 4 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆21Updated last year
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆38Updated 2 years ago
- HDL code for a complex multiplier with AXI stream Interface☆13Updated last year
- Fixed-point math library with VHDL, Python and MATLAB support☆18Updated 5 months ago
- HDL code for a complex multiplier with AXI stream interface☆16Updated last year
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆32Updated 4 months ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆51Updated 10 months ago
- Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.☆58Updated last month
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆59Updated last year
- Board files to build the ZCU111 PYNQ image☆18Updated 2 years ago
- Vitis Model Composer Examples and Tutorials☆80Updated this week
- Extensible FPGA control platform☆55Updated last year
- Dual-Mode PSK Transceiver on SDR With FPGA☆23Updated 3 months ago
- ☆32Updated last year