Xilinx / RFSoC2x2-PYNQ
RFSoC2x2 board repo for PYNQ
☆17Updated 2 years ago
Alternatives and similar repositories for RFSoC2x2-PYNQ:
Users that are interested in RFSoC2x2-PYNQ are comparing it to the libraries listed below
- An RFSoC Frequency Planner developed using Python.☆21Updated last year
- A collection of RFSoC introductory notebooks for PYNQ.☆19Updated 3 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆97Updated last year
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆45Updated last year
- Demonstration of Automatic Gain Control with PYNQ☆12Updated 2 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆17Updated 3 months ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆27Updated 2 years ago
- ☆18Updated 3 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆71Updated 7 months ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 2 years ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆32Updated last year
- Board repo for the ZCU216 RFSOC☆25Updated 2 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆39Updated 2 years ago
- Python productivity for RFSoC platforms☆63Updated 9 months ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆23Updated last year
- Open-sourcing the PYNQ & RFSoC workshop materials☆58Updated 4 years ago
- Companion Jupyter Notebooks for the RFSoC-Book.☆161Updated last year
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 3 weeks ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.☆60Updated this week
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆51Updated 11 months ago
- HDL code for a complex multiplier with AXI stream Interface☆13Updated last year
- MATLAB toolbox for ADI transceiver products☆59Updated 2 months ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆59Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- A collection of phase locked loop (PLL) related projects☆101Updated last year
- HDL code for a complex multiplier with AXI stream interface☆16Updated 2 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆93Updated 7 months ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆52Updated last week