strath-sdr / rfsoc_studioLinks
The Strathclyde RFSoC Studio Installer for PYNQ.
☆34Updated 2 years ago
Alternatives and similar repositories for rfsoc_studio
Users that are interested in rfsoc_studio are comparing it to the libraries listed below
Sorting:
- An RFSoC Frequency Planner developed using Python.☆31Updated 2 years ago
- Python productivity for RFSoC platforms☆84Updated 2 weeks ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆108Updated 2 years ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆40Updated 2 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆87Updated last year
- Demonstration of Automatic Gain Control with PYNQ☆16Updated 3 years ago
- ☆19Updated 4 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆55Updated 2 years ago
- RFSoC2x2 board repo for PYNQ☆17Updated 3 years ago
- Board repo for the ZCU216 RFSOC☆30Updated 3 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆30Updated 2 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆25Updated 11 months ago
- A collection of RFSoC introductory notebooks for PYNQ.☆24Updated 4 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆58Updated last year
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆40Updated 3 years ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆63Updated 5 years ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 3 years ago
- Companion Jupyter Notebooks for the RFSoC-Book.☆239Updated 2 years ago
- A collection of phase locked loop (PLL) related projects☆112Updated last year
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆77Updated 2 years ago
- Vitis Model Composer Examples and Tutorials☆108Updated this week
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆28Updated 4 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆67Updated last week
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆67Updated 4 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Gaussian noise generator Verilog IP core☆32Updated 2 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆124Updated last week
- Verilog digital signal processing components☆159Updated 3 years ago
- Learn how to deploy an algorithm to an FPGA using MATLAB and Simulink.☆86Updated 10 months ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated last week