sarafs1926 / ZCU216-PYNQ
Board repo for the ZCU216 RFSOC
☆26Updated 2 years ago
Alternatives and similar repositories for ZCU216-PYNQ:
Users that are interested in ZCU216-PYNQ are comparing it to the libraries listed below
- Open-sourcing the PYNQ & RFSoC workshop materials☆58Updated 4 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆100Updated last year
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆23Updated last year
- The Strathclyde RFSoC Studio Installer for PYNQ.☆30Updated 2 years ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 2 years ago
- ☆19Updated 3 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆39Updated 2 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆76Updated 9 months ago
- Python productivity for RFSoC platforms☆65Updated 10 months ago
- An RFSoC Frequency Planner developed using Python.☆24Updated last year
- RFSoC QSFP Data Offload Design with GNU Radio☆18Updated 4 months ago
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- A collection of RFSoC introductory notebooks for PYNQ.☆20Updated 3 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆151Updated 3 years ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆34Updated last year
- 10G Low Latency Ethernet☆48Updated last year
- A collection of phase locked loop (PLL) related projects☆103Updated last year
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆46Updated last year
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆59Updated 3 years ago
- Board files to build the ZCU111 PYNQ image☆18Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆55Updated 2 weeks ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆48Updated 3 years ago
- FPGA and Digital ASIC Build System☆74Updated last week
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆51Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.☆63Updated last month
- Networking Overlay on PYNQ☆48Updated 6 years ago
- Extensible FPGA control platform☆59Updated last year
- A tool for merging the MyHDL workflow with Vivado☆20Updated 4 years ago
- Demonstration of Automatic Gain Control with PYNQ☆12Updated 2 years ago