sarafs1926 / ZCU216-PYNQ
Board repo for the ZCU216 RFSOC
☆25Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for ZCU216-PYNQ
- Open-sourcing the PYNQ & RFSoC workshop materials☆56Updated 4 years ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 2 years ago
- ☆18Updated 3 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆26Updated last year
- PYNQ example of using the RFSoC as a QPSK transceiver.☆90Updated last year
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- Python productivity for RFSoC platforms☆55Updated 5 months ago
- Demonstration of Automatic Gain Control with PYNQ☆11Updated 2 years ago
- Board files to build the ZCU111 PYNQ image☆17Updated 2 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆20Updated last year
- RFSoC QSFP Data Offload Design with GNU Radio☆15Updated 5 months ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆37Updated 2 years ago
- A collection of RFSoC introductory notebooks for PYNQ.☆19Updated 3 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆69Updated 4 months ago
- An RFSoC Frequency Planner developed using Python.☆20Updated last year
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆39Updated 6 years ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆30Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆42Updated 11 months ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆50Updated 3 years ago
- A collection of phase locked loop (PLL) related projects☆99Updated 9 months ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆44Updated last year
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆22Updated 3 months ago
- Verilog digital signal processing components☆104Updated 2 years ago
- Companion Jupyter Notebooks for the RFSoC-Book.☆147Updated last year
- migen + misoc + redpitaya = digital servo☆35Updated 5 years ago
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆35Updated 5 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆142Updated 2 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆45Updated 6 months ago
- A testbench for an axi lite custom IP☆22Updated 9 years ago
- 10G Low Latency Ethernet☆40Updated last year