RealDigitalOrg / RFSoC4x2-BSPLinks
☆23Updated 3 months ago
Alternatives and similar repositories for RFSoC4x2-BSP
Users that are interested in RFSoC4x2-BSP are comparing it to the libraries listed below
Sorting:
- RFSoC QSFP Data Offload Design with GNU Radio☆25Updated last year
- An RFSoC Frequency Planner developed using Python.☆31Updated 2 years ago
- RFSoC2x2 board repo for PYNQ☆17Updated 3 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆109Updated 2 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆89Updated last year
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆57Updated 2 years ago
- Python productivity for RFSoC platforms☆85Updated last month
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆40Updated 2 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆34Updated 2 years ago
- Companion Jupyter Notebooks for the RFSoC-Book.☆246Updated 2 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆127Updated last month
- The USRP™ Hardware Driver FPGA Repository☆294Updated 4 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆125Updated 4 years ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆63Updated 5 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆31Updated 2 years ago
- Demonstration of Automatic Gain Control with PYNQ☆16Updated 3 years ago
- A collection of RFSoC introductory notebooks for PYNQ.☆25Updated 4 years ago
- SDK for FPGA / Linux Instruments☆107Updated last month
- RTL implementation of components for DVB-S2☆130Updated 2 years ago
- A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC☆39Updated last year
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆59Updated last year
- Board repo for the ZCU216 RFSOC☆31Updated 3 years ago
- Learn how to deploy an algorithm to an FPGA using MATLAB and Simulink.☆87Updated 11 months ago
- A configurable C++ generator of pipelined Verilog FFT cores☆251Updated last year
- MATLAB toolbox for ADI transceiver products☆64Updated last month
- A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog☆219Updated 7 months ago
- Open source AMD Xilinx Kria UltraScale+ SoM baseboard☆60Updated 11 months ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆61Updated 6 years ago
- A basic Soft(Gate)ware Defined Radio architecture☆100Updated last year
- Vitis Model Composer Examples and Tutorials☆112Updated last week