strath-sdr / rfsoc_samLinks
RFSoC Spectrum Analyser Module on PYNQ.
☆84Updated last year
Alternatives and similar repositories for rfsoc_sam
Users that are interested in rfsoc_sam are comparing it to the libraries listed below
Sorting:
- PYNQ example of using the RFSoC as a QPSK transceiver.☆105Updated 2 years ago
- An RFSoC Frequency Planner developed using Python.☆30Updated 2 years ago
- Python productivity for RFSoC platforms☆79Updated 2 months ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆50Updated 2 years ago
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆32Updated 2 years ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆37Updated 2 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆23Updated 9 months ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 3 years ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆62Updated 4 years ago
- Companion Jupyter Notebooks for the RFSoC-Book.☆221Updated 2 years ago
- Demonstration of Automatic Gain Control with PYNQ☆15Updated 3 years ago
- Repository for FPGA projects☆55Updated 10 months ago
- A collection of RFSoC introductory notebooks for PYNQ.☆23Updated 3 years ago
- Board repo for the ZCU216 RFSOC☆29Updated 3 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆115Updated last year
- A collection of phase locked loop (PLL) related projects☆108Updated last year
- RTL implementation of components for DVB-S2☆121Updated 2 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆39Updated 3 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆88Updated 2 years ago
- SDK for FPGA / Linux Instruments☆102Updated last week
- A basic Soft(Gate)ware Defined Radio architecture☆93Updated last year
- Learn how to deploy an algorithm to an FPGA using MATLAB and Simulink.☆83Updated 7 months ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆116Updated 4 years ago
- A collection of demonstration digital filters☆155Updated last year
- ☆19Updated 3 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆26Updated 2 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- ☆19Updated 4 months ago
- A FPGA accelerated SDR receiver using PYNQ-Z2 board and RTL-SDR☆22Updated 5 years ago