strath-sdr / rfsoc_sam

Related projects: ⓘ

• strath-sdr / rfsoc_qpsk
  PYNQ example of using the RFSoC as a QPSK transceiver.
  ☆88Updated last year
• Xilinx / RFSoC-PYNQ
  Python productivity for RFSoC platforms
  ☆52Updated 3 months ago
• strath-sdr / rfsoc_notebooks
  A collection of RFSoC introductory notebooks for PYNQ.
  ☆19Updated 2 years ago
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated last year
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆18Updated last year
• Xilinx / PYNQ_RFSOC_Workshop
  Open-sourcing the PYNQ & RFSoC workshop materials
  ☆56Updated 3 years ago
• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆44Updated last year
• strath-sdr / RFSoC-Book
  Companion Jupyter Notebooks for the RFSoC-Book.
  ☆136Updated last year
• Xilinx / SDFEC-PYNQ
  A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC
  ☆13Updated 2 years ago
• sarafs1926 / ZCU216-PYNQ
  Board repo for the ZCU216 RFSOC
  ☆25Updated 2 years ago
• strath-sdr / pynq_agc
  Demonstration of Automatic Gain Control with PYNQ
  ☆11Updated 2 years ago
• strath-sdr / rfsoc_qsfp_offload
  RFSoC QSFP Data Offload Design with GNU Radio
  ☆14Updated 3 months ago
• strath-sdr / rfsoc_radio
  PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.
  ☆29Updated last year
• Xilinx / DSP-PYNQ
  A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
  ☆36Updated 2 years ago
• strath-sdr / rfsoc_studio
  The Strathclyde RFSoC Studio Installer for PYNQ.
  ☆26Updated last year
• wady101 / PYNQ_Z2-Audio
  Audio streaming architecture for the PYNQ-Z2 board
  ☆9Updated 5 years ago
• RedPitaya / RedPitaya-FPGA
  Repository for FPGA projects
  ☆35Updated last month
• JennySmith888 / 100GBE-PYNQ
  ☆18Updated 3 years ago
• MazinLab / RFSoC_OPFB
  A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC
  ☆23Updated last week
• dshekhalev / FEC
  FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
  ☆84Updated 2 months ago
• Xilinx / Vitis_Model_Composer
  Vitis Model Composer Examples and Tutorials
  ☆70Updated this week
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆95Updated 8 months ago
• dspsandbox / Pynq-Redpitaya-125
  ☆18Updated last year
• Xilinx / ZCU111-PYNQ
  Board files to build the ZCU111 PYNQ image
  ☆17Updated last year
• efard / DSPHDL
  ☆40Updated 6 months ago
• marsiau / PYNQ-RTL-SDR
  A FPGA accelerated SDR receiver using PYNQ-Z2 board and RTL-SDR
  ☆18Updated 4 years ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated last year
• madamic / zynq_tdc
  A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
  ☆47Updated 3 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆52Updated last week
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆28Updated 5 years ago