strath-sdr / rfsoc_samLinks
RFSoC Spectrum Analyser Module on PYNQ.
☆87Updated last year
Alternatives and similar repositories for rfsoc_sam
Users that are interested in rfsoc_sam are comparing it to the libraries listed below
Sorting:
- PYNQ example of using the RFSoC as a QPSK transceiver.☆109Updated 2 years ago
- An RFSoC Frequency Planner developed using Python.☆31Updated 2 years ago
- Python productivity for RFSoC platforms☆84Updated last month
- RFSoC2x2 board repo for PYNQ☆17Updated 3 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆34Updated 2 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆56Updated 2 years ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆40Updated 2 years ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆63Updated 5 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆40Updated 3 years ago
- A collection of RFSoC introductory notebooks for PYNQ.☆24Updated 4 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆25Updated last year
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 3 years ago
- Repository for FPGA projects☆57Updated this week
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆124Updated 4 years ago
- Board repo for the ZCU216 RFSOC☆30Updated 3 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆86Updated 2 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆124Updated 2 weeks ago
- Demonstration of Automatic Gain Control with PYNQ☆16Updated 3 years ago
- A collection of phase locked loop (PLL) related projects☆112Updated last year
- Companion Jupyter Notebooks for the RFSoC-Book.☆241Updated 2 years ago
- A FPGA accelerated SDR receiver using PYNQ-Z2 board and RTL-SDR☆22Updated 6 years ago
- SDK for FPGA / Linux Instruments☆107Updated 3 weeks ago
- ☆19Updated 4 years ago
- A collection of demonstration digital filters☆161Updated last year
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆59Updated last year
- ☆20Updated 7 months ago
- RTL implementation of components for DVB-S2☆129Updated 2 years ago
- A configurable C++ generator of pipelined Verilog FFT cores☆251Updated last year
- A basic Soft(Gate)ware Defined Radio architecture☆100Updated last year
- A Python package to use FPGA development tools programmatically.☆143Updated 8 months ago