strath-sdr / rfsoc_radioLinks
PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.
☆37Updated 2 years ago
Alternatives and similar repositories for rfsoc_radio
Users that are interested in rfsoc_radio are comparing it to the libraries listed below
Sorting:
- Python productivity for RFSoC platforms☆78Updated 3 weeks ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆32Updated 2 years ago
- An RFSoC Frequency Planner developed using Python.☆29Updated 2 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆50Updated 2 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆103Updated 2 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆82Updated last year
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- Demonstration of Automatic Gain Control with PYNQ☆15Updated 3 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆22Updated 7 months ago
- Companion Jupyter Notebooks for the RFSoC-Book.☆208Updated 2 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆25Updated 2 years ago
- A collection of phase locked loop (PLL) related projects☆107Updated last year
- Board repo for the ZCU216 RFSOC☆29Updated 3 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆39Updated 3 years ago
- A collection of RFSoC introductory notebooks for PYNQ.☆23Updated 3 years ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆62Updated 4 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆109Updated last year
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 3 years ago
- ☆19Updated 3 years ago
- Learn how to deploy an algorithm to an FPGA using MATLAB and Simulink.☆78Updated 6 months ago
- A basic Soft(Gate)ware Defined Radio architecture☆88Updated last year
- FPGA and Digital ASIC Build System☆74Updated this week
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆88Updated 2 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆115Updated 4 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆62Updated last week
- A collection of demonstration digital filters☆154Updated last year
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆71Updated 2 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- Vitis Model Composer Examples and Tutorials☆102Updated last month
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆51Updated this week