ReaLLMASIC / ReaLLM-ForgeLinks
A Framework for Hardware-Aware LLM Exploration
☆37Updated last week
Alternatives and similar repositories for ReaLLM-Forge
Users that are interested in ReaLLM-Forge are comparing it to the libraries listed below
Sorting:
- IC implementation of Systolic Array for TPU☆314Updated last year
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆171Updated last month
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆122Updated 4 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆177Updated 6 years ago
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆104Updated last month
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆30Updated 2 years ago
- DRA+RISC-V Exploration Framework☆18Updated last year
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆218Updated last year
- ☆123Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆109Updated 5 years ago
- Research and Materials on Hardware implementation of Transformer Model☆292Updated 9 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆143Updated 7 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆70Updated 5 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆139Updated 10 months ago
- IC implementation of TPU☆142Updated 6 years ago
- Verilog implementation of Softmax function☆78Updated 3 years ago
- ai_accelerator_basic_for_student (no solve)☆12Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆236Updated 2 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆205Updated 5 years ago
- ☆21Updated 2 months ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆108Updated 11 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆275Updated last week
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆100Updated last week
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆148Updated this week
- A Fast, Low-Overhead On-chip Network☆251Updated this week
- Deep Learning Accelerator (Convolution Neural Networks)☆196Updated 8 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆73Updated last month
- Library of approximate arithmetic circuits☆61Updated 3 years ago
- ☆45Updated 4 years ago