Alternatives and similar repositories for ZynqOLED

Users that are interested in ZynqOLED are comparing it to the libraries listed below

• Verdvana / OV5640_SDRAM
  OV5640摄像头驱动及TFT屏幕显示
  ☆16Updated 6 years ago
• nour176yj / FIR-LPF-Digital-Design-
  A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ
  ☆14Updated 2 years ago
• AhmadGon / WM8731-Audio-CODEC
  WM8731 Audio CODEC using Verilog (DE2-115)
  ☆10Updated 6 years ago
• sujan2599 / LMS-Adaptive-FIR-Filter
  design of LMS adaptive 4-tap FIR filter using Distributed Arithmetic architecture in verilog
  ☆10Updated 3 years ago
• chenshuo / veriloglabs
  Undergraduate digital circuit laboratory
  ☆28Updated 2 years ago
• suisuisi / AXI4-Stream-FIR-filter
  AXI4-Stream FIR filter IP
  ☆19Updated 3 years ago
• Digilent / Zedboard-DMA
  ☆13Updated 6 years ago
• Reenforcements / VerilogDE2115AudioFilters
  Student project for using audio on the DE2-115 FPGA development board.
  ☆27Updated 7 years ago
• maxs-well / FIR_Implementation
  FIR filter implementation
  ☆29Updated 5 years ago
• MostafaOkasha / ECHO-and-FIR-FILTER-implementation-on-Verilog-HDL
  Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…
  ☆10Updated 6 years ago
• padhi499 / Image-Classification-using-CNN-on-FPGA
  Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
  ☆163Updated 5 years ago
• suisuisi / FPGAandStudy
  帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
  ☆37Updated 3 years ago
• Digilent / Zybo-hdmi-in
  ☆12Updated 8 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆152Updated 6 years ago
• AngeloJacobo / FPGA_RealTime_and_Static_Sobel_Edge_Detection
  Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
  ☆66Updated 4 years ago
• Digilent / Nexys-A7-100T-OOB
  ☆31Updated 5 years ago
• ivanvig / 2dconv-FPGA
  A 2D convolution hardware implementation written in Verilog
  ☆51Updated 5 years ago
• DOUDIU / Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm
  The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…
  ☆45Updated last year
• lijiaxun-sgms / w25q128jvxim_v_sim
  Verilog Model for W25Q128JVxIM Serial Flash Memory
  ☆16Updated 5 years ago
• vipinkmenon / neuralNetwork
  ☆299Updated last year
• C-H-Chien / FPGA_SIFT-LES
  Integration of SIFT and LES Algorithms
  ☆14Updated last year
• Giftwen / DC_script
  syn script for DC Compiler
  ☆14Updated 3 years ago
• MaharshSuryawala / Image-Compression
  Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.
  ☆17Updated 5 years ago
• ATaylorCEngFIET / Hackster
  Files used with hackster examples
  ☆149Updated 5 years ago
• medalotte / HLS-canny-edge-detection
  FPGA implementation of Canny edge detection by using Vivado HLS
  ☆55Updated 6 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆57Updated 11 years ago
• BambooWhispering / FPGA-image-simulation
  FPGA图像处理仿真平台
  ☆28Updated 3 years ago
• gillianGan / ahb_sram_master
  ☆19Updated 5 years ago
• georgeyhere / FPGA-Video-Processing
  Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
  ☆32Updated 4 years ago
• suisuisi / Accelerating-CNN-with-FPGA
  This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
  ☆24Updated 6 years ago