Alternatives and similar repositories for vhdl-style-guide

Users that are interested in vhdl-style-guide are comparing it to the libraries listed below

• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆189Updated 2 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆179Updated this week
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆248Updated last month
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆396Updated last week
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆406Updated last week
• kevinpt / symbolator
  HDL symbol generator
  ☆193Updated 2 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆126Updated 3 months ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆161Updated 3 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆62Updated 4 years ago
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆588Updated last month
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆143Updated 2 weeks ago
• svunit / svunit
  ☆206Updated 6 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 7 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 7 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆229Updated last week
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆281Updated this week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆116Updated last year
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated last year
• rggen / rggen
  Code generation tool for control and status registers
  ☆421Updated 3 weeks ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆55Updated 2 months ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆135Updated last year
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆281Updated 5 years ago
• Lramseyer / vaporview
  Waveform Viewer Extension for VScode
  ☆252Updated last week
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆76Updated last week
• raysalemi / Python4RTLVerification
  ☆164Updated 3 years ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆416Updated last week
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated last month
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆65Updated last month
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆235Updated last year