Alternatives and similar repositories for vhdl-style-guide:

Users that are interested in vhdl-style-guide are comparing it to the libraries listed below

• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆182Updated last year
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆232Updated 2 weeks ago
• slaclab / surf
  A huge VHDL library for FPGA development
  ☆365Updated this week
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆131Updated this week
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆383Updated last week
• kevinpt / symbolator
  HDL symbol generator
  ☆186Updated last year
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆112Updated 3 weeks ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆108Updated this week
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆411Updated this week
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆274Updated 5 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆221Updated last year
• themperek / cocotb-test
  Unit testing for cocotb
  ☆153Updated 2 weeks ago
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆221Updated 7 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆507Updated last week
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 8 years ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆316Updated 3 weeks ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆64Updated last year
• raysalemi / Python4RTLVerification
  ☆130Updated 2 years ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆143Updated this week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆106Updated last year
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆81Updated 6 months ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆585Updated 2 weeks ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆346Updated this week
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆51Updated 3 months ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆32Updated last month
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆562Updated 4 years ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆195Updated 2 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 6 months ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆276Updated this week