☆56Oct 24, 2022Updated 3 years ago
Alternatives and similar repositories for wokwi-verilog-gds-test
Users that are interested in wokwi-verilog-gds-test are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Riegel Computer☆17Jun 30, 2023Updated 3 years ago
- ☆20May 25, 2026Updated last month
- TinyTapeout-01 submission repo☆32Nov 28, 2022Updated 3 years ago
- Submission template for Tiny Tapeout 03☆22Sep 20, 2023Updated 2 years ago
- ☆17Aug 16, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A ZipCPU demonstration port for the icoboard☆19Oct 21, 2021Updated 4 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆53Feb 22, 2022Updated 4 years ago
- The code for an FPGA softcore comparison☆11Jun 21, 2020Updated 6 years ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆164Jun 1, 2024Updated 2 years ago
- Tiny, Ultra-low-power UWB Localization Tag based on DWM1000 and STM32L031☆11Jun 10, 2019Updated 7 years ago
- simple wishbone client to read buttons and write leds☆19Nov 30, 2023Updated 2 years ago
- AD9363 + XC6SLX9 board☆12Apr 23, 2019Updated 7 years ago
- Latest in the line of the E32 processors with better/generic cache placement☆10Feb 25, 2023Updated 3 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Reusable 4-bit CPU in Logisim with Verilog HDL, ISA docs, and a browser playground☆14Feb 24, 2026Updated 4 months ago
- ☆44Feb 12, 2021Updated 5 years ago
- This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL☆20Feb 23, 2020Updated 6 years ago
- LunaPnR is a place and router for integrated circuits☆48Feb 11, 2026Updated 5 months ago
- PLEASE MOVE TO PAWSv2☆16Feb 2, 2022Updated 4 years ago
- Repository for VSD-IAT Workshop: Physical Verification using SKY130☆10Aug 15, 2021Updated 4 years ago
- USB DFU bootloader gateware / firmware for FPGAs☆71Jan 30, 2026Updated 5 months ago
- Tiny Tapeout 06☆16Nov 15, 2025Updated 8 months ago
- The Ghost blog system upgraded with Heroku deploys & IPFS support.☆15Dec 10, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Development board for GateMateA1 CCGM1A1 FPGA from Cologne Chip with PS2 VGA 64Mbit RAM RP2040☆44Mar 24, 2026Updated 3 months ago
- ☆17Jun 27, 2021Updated 5 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 5 months ago
- Converts GDSII files to STL files.☆43Dec 12, 2023Updated 2 years ago
- IHP Open source SG13G2 Tape Out on April 2025 [Testfield T586]☆17Apr 27, 2026Updated 2 months ago
- Completed LDO Design for Skywaters 130nm☆20Feb 16, 2023Updated 3 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆73May 13, 2026Updated 2 months ago
- USB capture IP☆26Jun 6, 2020Updated 6 years ago
- ☆23Oct 19, 2021Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Test Chip General Purpose OpAmp using Skywater SKY130 PDK☆20Mar 1, 2021Updated 5 years ago
- Ubuntu scripts that are used for setting up your machine for Sky130 designs.☆18Mar 18, 2021Updated 5 years ago
- ☆18Nov 4, 2024Updated last year
- pLUTo is a DRAM-based Processing-using-Memory architecture that leverages the high density of DRAM to enable the massively parallel stori…☆20Jan 12, 2023Updated 3 years ago
- Virtual development board for HDL design☆42Mar 31, 2023Updated 3 years ago
- ☆36Nov 2, 2023Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆60Dec 19, 2022Updated 3 years ago