Alternatives and similar repositories for fpga_fifo

Users that are interested in fpga_fifo are comparing it to the libraries listed below

• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆50Updated 8 months ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 4 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆33Updated 4 years ago
• ZipCPU / interpolation
  Digital Interpolation Techniques Applied to Digital Signal Processing
  ☆62Updated last year
• 0xArt / Tiny_But_Mighty_I2C_Master_Verilog
  I2C Master Verilog module
  ☆34Updated last month
• krtkl / snickerdoodle-hls-data-mover
  A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…
  ☆14Updated 6 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 5 months ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆91Updated 5 years ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆38Updated 4 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆28Updated 5 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆46Updated last year
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆32Updated 4 years ago
• jlublin / xvcd_server
  Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters
  ☆11Updated 11 years ago
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆13Updated 7 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆47Updated last week
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆23Updated 4 years ago
• hukenovs / adc_configurator
  ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
  ☆12Updated 6 years ago
• noasic / noasic
  An open-source VHDL library for FPGA design.
  ☆31Updated 3 years ago
• skristiansson / wb_sdram_ctrl
  SDRAM controller with multiple wishbone slave ports
  ☆29Updated 6 years ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• MJoergen / HyperRAM
  Portable HyperRAM controller
  ☆56Updated 7 months ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆65Updated last week
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated 2 years ago
• emard / flearadio
  Digital FM Radio Receiver for FPGA
  ☆61Updated 9 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆34Updated 4 months ago
• CoreyChen922 / sata_2_host_controller
  Sata 2 Host Controller for FPGA implementation
  ☆18Updated 7 years ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆42Updated 5 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆81Updated 4 years ago