FPGANinjas / nitefury_pcie_xdma_ddr

Related projects ⓘ

Alternatives and complementary repositories for nitefury_pcie_xdma_ddr

• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆35Updated 3 years ago
• aomtoku / hdmi-ts
  hdmi-ts Project
  ☆13Updated 7 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆26Updated 4 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆28Updated last month
• ultraembedded / cortex_m0_wrapper
  Cortex-M0 DesignStart Wrapper
  ☆17Updated 5 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆24Updated 3 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated 10 months ago
• freecores / wdsp
  DSP WishBone Compatible Cores
  ☆13Updated 10 years ago
• hukenovs / adc_configurator
  ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
  ☆12Updated 6 years ago
• siorpaes / BareBonesCortexM0
  Extremely basic CortexM0 SoC based on ARM DesignStart Eval
  ☆22Updated 6 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆31Updated 4 years ago
• ahmad2smile / SHA256_Verilog
  Verilog based FPGA Design of SHA256 Simulated on ModelSim
  ☆19Updated 6 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆54Updated last year
• slaclab / axi-pcie-core
  ☆20Updated last week
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆26Updated last month
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆20Updated 9 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• CospanDesign / python-pci
  Python interface to PCIE
  ☆38Updated 6 years ago
• aignacio / mpsoc_example
  ☆57Updated 3 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆24Updated 4 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆22Updated 4 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆35Updated 5 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆21Updated 6 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆36Updated 5 months ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• mnasser431998 / bfu_dif_fft_rtl
  The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
  ☆13Updated last year
• umarcor / hwstudio
  GUI editor for hardware description designs
  ☆27Updated last year