Alternatives and similar repositories for nitefury_pcie_xdma_ddr

Users that are interested in nitefury_pcie_xdma_ddr are comparing it to the libraries listed below

• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆40Updated 4 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆32Updated 9 years ago
• DUNE / pl-nvme
  ☆36Updated 5 years ago
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆29Updated 5 years ago
• pbridd / lzrw1-compression-core
  This is the repository for a verilog implementation of a lzrw1 compression core
  ☆18Updated 7 years ago
• mcrl / NVMe
  ☆35Updated last year
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆36Updated 5 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆41Updated 8 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆26Updated 3 weeks ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆26Updated 4 years ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆31Updated 5 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• akhan3 / async-fifo
  Asynchronous FIFO for transferring data between two asynchronous clock domains
  ☆18Updated 9 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆21Updated 8 years ago
• GOOD-Stuff / FPGA-SPI-Flash
  Various projects of SPI loader module for xilinx fpga
  ☆33Updated 5 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆28Updated 4 years ago
• ultraembedded / fpga_test_soc
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆34Updated 5 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆65Updated 3 years ago
• CospanDesign / python-pci
  Python interface to PCIE
  ☆40Updated 7 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆80Updated 3 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• fpgadeveloper / ethernet-fmc-processorless
  Example designs for using Ethernet FMC without a processor (ie. state machine based)
  ☆34Updated last year
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆51Updated last year
• AugustinJose1221 / FFTx32
  A 32 point radix-2 FFT module written in Verilog
  ☆23Updated 5 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆24Updated 7 years ago
• siorpaes / SimpleSoC
  Very simple Cortex-M1 SoC design based on ARM DesignStart
  ☆17Updated 3 years ago
• freecores / pipelined_fft_64
  Pipelined FFT/IFFT 64 points processor
  ☆11Updated 11 years ago
• mnasser431998 / bfu_dif_fft_rtl
  The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
  ☆15Updated 2 years ago