Alternatives and similar repositories for XT_RISC-V_Soc

Users that are interested in XT_RISC-V_Soc are comparing it to the libraries listed below

• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆126Updated last year
• Nitcloud / Digital-IDE
  在vscode上的数字设计开发插件
  ☆391Updated 2 years ago
• CutestPanda / Opensoc
  包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等
  ☆120Updated 2 months ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆32Updated 3 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆165Updated 3 years ago
• RV-BOSC / OpenNoC
  ☆214Updated 5 months ago
• RongyeL / EasyAXI
  ☆81Updated 2 weeks ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆153Updated 2 weeks ago
• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆367Updated 2 years ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆63Updated last year
• OSCPU / ysyx-workbench
  ☆159Updated 2 weeks ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆191Updated last year
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆176Updated 3 years ago
• OSCPU / ysyxSoC
  ☆91Updated 2 months ago
• Xinyang-ZHANG / RISC_V_RV32I_5stage_pipeline
  5 stage pipeline, single cycle risc-V implementation
  ☆26Updated last year
• WangXuan95 / USTC-RVSoC
  An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
  ☆420Updated 2 years ago
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆72Updated 2 years ago
• Digital-EDA / Digital-IDE
  All in one vscode plugin for HDL development
  ☆992Updated 6 months ago
• cxdzyq1110 / NPU_on_FPGA
  在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。
  ☆281Updated 7 years ago
• HonkW93 / automatic-verilog
  automatic-verilog based on vimscript
  ☆278Updated 2 years ago
• xiaop1 / Verilog-Practice
  HDLBits website practices & solutions
  ☆762Updated last year
• leesum1 / ysyx
  一生一芯项目
  ☆17Updated 2 years ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆326Updated 7 years ago
• riscv-mcu / hbird-sdk
  OpenSource HummingBird RISC-V Software Development Kit
  ☆167Updated 2 years ago
• tyxiumud / gvim_for_verilog
  this repository is vim cfg for verilog.
  ☆54Updated last year
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆25Updated 6 months ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆489Updated 5 years ago
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆121Updated 12 years ago
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆162Updated 11 months ago
• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆101Updated 11 months ago