一个极其简易的RV32I指令集单核MCU,用户级与特权级支持,仅运行机器模式。
☆67Oct 2, 2026Updated last week
Alternatives and similar repositories for XT_RISC-V_Soc
Users that are interested in XT_RISC-V_Soc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆28Sep 19, 2026Updated 3 weeks ago
- ☆18Aug 19, 2024Updated 2 years ago
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆14Mar 13, 2022Updated 4 years ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆35Aug 22, 2024Updated 2 years ago
- ☆20May 1, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛(龙芯杯)团队赛二等奖作品☆26Sep 14, 2024Updated 2 years ago
- biRISC-V - 32-bit dual issue RISC-V CPU Software Environment☆17Jun 24, 2021Updated 5 years ago
- ☆139May 30, 2026Updated 4 months ago
- ☆44Jul 28, 2025Updated last year
- APB Timer Unit☆14Oct 30, 2025Updated 11 months ago
- 对酒当歌晚长亭在B站的关于Vitis HLS的视频教程的源代码☆27Oct 28, 2025Updated 11 months ago
- Google's TRex mini game in Verilog on Xilinx Nexys3 FPGA☆12Mar 27, 2020Updated 6 years ago
- 安徽大学文典学院的笔记、经验和学习资料等。☆35Dec 26, 2024Updated last year
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆28Jun 30, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- CPU Design Based on RISCV ISA☆148Jun 14, 2024Updated 2 years ago
- riscv指令集,单周期以及五级流水线CPU☆138Jan 6, 2025Updated last year
- ☆43Apr 28, 2019Updated 7 years ago
- Clock Domain Crossing Design(use MCP formulation without feedback)基于MCP不带反馈的跨时钟域设计☆13Jan 3, 2020Updated 6 years ago
- 该文档是个人阅读学习蜂鸟E203源码的笔记☆15Aug 1, 2023Updated 3 years ago
- FPGA-based SATA-DMA Host Controller☆36Nov 20, 2025Updated 10 months ago
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆152Sep 17, 2026Updated 3 weeks ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- ☆13Aug 5, 2023Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆10Dec 15, 2023Updated 2 years ago
- 平头哥无剑100开源SoC平台(双核E902,安全启动,BootROM,IOPMP,Mailbox,RSA-2048,SHA-2, WS2812,Flash)☆23Sep 2, 2023Updated 3 years ago
- SJTU CS2951 Computer Architecture Course Project, A Verilog HDL implemented RISC-V CPU.☆11Jan 15, 2022Updated 4 years ago
- ☆11Apr 27, 2023Updated 3 years ago
- fpga读取摄像头数据上传到上位机,720P@60Hz☆20Mar 15, 2021Updated 5 years ago
- Projects for the Scarab Minispartan6+ FPGA board☆14Jun 20, 2015Updated 11 years ago
- https://caravel-user-project.readthedocs.io☆18Mar 29, 2022Updated 4 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Oct 2, 2026Updated last week
- 【笔记】计算机技术和嵌入式系统开发学习笔记。☆18Jul 16, 2026Updated 2 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆11Aug 2, 2024Updated 2 years ago
- Still in development...☆20Feb 26, 2017Updated 9 years ago
- ☆51Oct 6, 2024Updated 2 years ago
- 我设计了一些数字集成电路的教学实验,供大家学习~☆39Jan 23, 2025Updated last year
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆40Aug 13, 2024Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago