ankitshah009 / High-Radix-Adaptive-CORDIC
High Radix Adaptive CORDIC Algorithm - Improvement over Traditional CORDIC
☆12Updated 8 years ago
Related projects ⓘ
Alternatives and complementary repositories for High-Radix-Adaptive-CORDIC
- FFT implementation using CORDIC algorithm written in Verilog.☆29Updated 6 years ago
- FFT implement by verilog_测试验证已通过☆52Updated 8 years ago
- A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.☆13Updated 3 years ago
- Step by step tutorial for building CortexM0 SoC☆36Updated 2 years ago
- ☆34Updated 9 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆55Updated 3 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆31Updated 2 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 4 years ago
- SDRAM controller with AXI4 interface☆78Updated 5 years ago
- configurable cordic core in verilog☆47Updated 10 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆24Updated 3 years ago
- Interface Protocol in Verilog☆47Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- AXI Interconnect☆46Updated 3 years ago
- RTL Verilog library for various DSP modules☆83Updated 2 years ago
- upgrade to e203 (a risc-v core)☆37Updated 4 years ago
- Generic AXI to AHB bridge☆15Updated 10 years ago
- UART -> AXI Bridge☆58Updated 3 years ago
- SPI interface connect to APB BUS with Verilog HDL☆25Updated 3 years ago
- AXI总线连接器