Alternatives and similar repositories for High-Radix-Adaptive-CORDIC

Users that are interested in High-Radix-Adaptive-CORDIC are comparing it to the libraries listed below

• Muhazam-Mustapha / SqrtCORDIC
  A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.
  ☆17Updated 4 years ago
• JoshuaEbenezer / FFT-cordic-HDL
  FFT implementation using CORDIC algorithm written in Verilog.
  ☆33Updated 6 years ago
• freecores / verilog_cordic_core
  configurable cordic core in verilog
  ☆52Updated 11 years ago
• erbanhun / ZTE_DPD
  ☆11Updated 7 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆60Updated 8 years ago
• Starrynightzyq / Delta-Sigma-Modulator
  Delta-Sigma modulator (DSM) for fractional phase locked loop.
  ☆30Updated 4 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆90Updated 3 years ago
• cassuto / CORDIC-all-in-one-verilog
  FPGA version of CORDIC algorithm that evaluates all the trigonometric and anti-trigonometric functions.
  ☆23Updated 5 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆72Updated 3 years ago
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆38Updated 3 years ago
• cjhonlyone / NandFlashController
  AXI Interface Nand Flash Controller (Sync mode)
  ☆96Updated last year
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 5 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆96Updated 6 years ago
• WangXuan95 / FPGA-DDR-SDRAM
  An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
  ☆188Updated last year
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 10 years ago
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆36Updated 4 years ago
• WangXuan95 / FPGA-FixedPoint
  Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…
  ☆203Updated last year
• BigPig-Bro / udp_gmii_ov5640
  本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛（高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。
  ☆51Updated last year
• RongyeL / EasyAXI
  ☆58Updated last week
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆68Updated 5 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆131Updated 6 years ago
• WangXuan95 / FPGA-Gzip-compressor
  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …
  ☆136Updated last year
• filipamator / adpll
  All digital PLL
  ☆28Updated 7 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆66Updated last year
• maxs-well / USB_Ctrl
  USB2.0 Verilog
  ☆18Updated 6 years ago
• maxs-well / FIR_Implementation
  FIR filter implementation
  ☆27Updated 5 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• maxs-well / LMS-sound-filtering-by-Verilog
  LMS sound filtering by Verilog
  ☆41Updated 5 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆66Updated last year
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆103Updated 5 years ago