amiq-consulting / image-upscaling-CNN
How to Accelerate an Image Upscaling CNN on FPGA Using HLS
☆24Updated 3 years ago
Alternatives and similar repositories for image-upscaling-CNN:
Users that are interested in image-upscaling-CNN are comparing it to the libraries listed below
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆30Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 7 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆30Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆61Updated 8 months ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆8Updated last year
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆71Updated last year
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- ☆63Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- 文档编写☆12Updated 4 years ago
- Some attempts to build CNN on PYNQ.☆24Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- ☆31Updated 5 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆33Updated 5 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- DMA controller for CNN accelerator☆13Updated 7 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- tpu-systolic-array-weight-stationary☆24Updated 3 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- ☆50Updated 2 years ago
- ☆45Updated 6 years ago