amiq-consulting / image-upscaling-CNN
How to Accelerate an Image Upscaling CNN on FPGA Using HLS
☆20Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for image-upscaling-CNN
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆9Updated last year
- Convolutional Neural Network Implemented in Verilog for System on Chip☆24Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆21Updated 2 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆29Updated 5 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆32Updated 2 months ago
- DMA controller for CNN accelerator☆12Updated 7 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆30Updated 2 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆29Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆18Updated 7 years ago
- Hardware accelerator for convolutional neural networks☆26Updated 2 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆12Updated 3 years ago
- tpu-systolic-array-weight-stationary☆19Updated 3 years ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆21Updated last year
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆83Updated 4 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆10Updated 3 years ago
- ☆13Updated last year
- ☆26Updated 5 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆47Updated 6 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆49Updated 7 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆24Updated 3 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 3 years ago
- CNN accelerator using NoC architecture☆15Updated 5 years ago
- Zynq-7000 DPU TRD☆43Updated 5 years ago
- ☆50Updated 5 months ago
- Convolution Neural Network of vgg19 model in verilog☆44Updated 6 years ago