FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.
☆15Jul 19, 2012Updated 13 years ago
Alternatives and similar repositories for Verilog-Spectrum-Analyzer
Users that are interested in Verilog-Spectrum-Analyzer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Identifies ASL Hand Gesture for numbers using image processing in verilog☆14May 3, 2012Updated 13 years ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆16Jan 10, 2018Updated 8 years ago
- SERDES-based TDC core for Spartan-6☆19Aug 2, 2012Updated 13 years ago
- A place to store the code for FPGA tutorial projects I have written for the Parallella [http://parallellagram.org]☆11Oct 19, 2014Updated 11 years ago
- The code for paper -- 'PCF-Grasp: Converting Point Completion to Geometry Feature to Enhance 6-DoF Grasp'☆16Dec 15, 2025Updated 3 months ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions.…☆31Feb 9, 2018Updated 8 years ago
- Implementation of different types of adder circuits☆16Jan 5, 2016Updated 10 years ago
- A new CASPER toolflow based on an HDL primitives library☆17Apr 11, 2012Updated 13 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Jan 7, 2016Updated 10 years ago
- FPGA development platform for high-performance RF and digital design☆32Dec 3, 2015Updated 10 years ago
- Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determine…☆15Jun 15, 2016Updated 9 years ago
- 对16QAM信号进行解调,同步头的提取,解调出同相和正交信号,将滤波后的I路和Q路信号叠加,画出星座图,再对星座图的偏移进行纠正☆11Mar 22, 2021Updated 5 years ago
- RiscSoC 是一个芯片集成项目,包含了 Cortex-M0、Cortex-M3、MIPS 、RISC-V、4-BIT 等内核的 SoC 集成,部分 SoC 使用的自己设计的内核☆12Apr 26, 2022Updated 3 years ago
- A simple low-resource usage Kalman Filter using shared resources - in MyHDL☆10Oct 7, 2024Updated last year
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- FPGA based modular synth.☆19Jan 8, 2017Updated 9 years ago
- Implementing the Double-Slit experiment in Python☆12Jan 7, 2021Updated 5 years ago
- Yet another IPython notebook to LaTeX converter - this one exports clean code easily absorbed in other reports.☆16Jun 1, 2023Updated 2 years ago
- Verilog FPGA code : including experimental DSP audio processor☆13Dec 1, 2020Updated 5 years ago
- An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)☆76Jun 7, 2012Updated 13 years ago
- ☆30Feb 4, 2021Updated 5 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Provides a VXI-11 driver for controlling instruments over Ethernet☆14May 11, 2017Updated 8 years ago
- Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. …☆15Jan 19, 2018Updated 8 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)☆10Jan 9, 2016Updated 10 years ago
- Complete simulation of IEEE 754 fixed and floating point specification to any precision☆12Aug 26, 2020Updated 5 years ago
- MyBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in MyHDL (http://www.myhdl.org). It started as a translation of…☆17May 30, 2013Updated 12 years ago
- A very simple UART implementation in MyHDL☆17Aug 21, 2014Updated 11 years ago
- hdmi-ts Project☆13Jun 11, 2017Updated 8 years ago
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆22May 24, 2023Updated 2 years ago
- ShipAI simplified to medium tutorial☆16Dec 12, 2018Updated 7 years ago
- RetroCade Synth - C64 SID, YM2149, and POKEY audio chips with MIDI interface.☆39Jan 5, 2017Updated 9 years ago
- 异步FIFO的内部实现☆25Aug 26, 2018Updated 7 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- myhdl.org website☆13Dec 22, 2024Updated last year
- Zedboard projects☆11May 15, 2016Updated 9 years ago
- Utilities for MyHDL☆19Dec 15, 2023Updated 2 years ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆25Mar 9, 2016Updated 10 years ago
- An open source hardware engine for Open vSwitch on FPGA☆26Dec 8, 2012Updated 13 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago
- mirror of https://git.elphel.com/Elphel/x393☆40Mar 16, 2023Updated 3 years ago