Alternatives and similar repositories for Verilog-Spectrum-Analyzer

Users that are interested in Verilog-Spectrum-Analyzer are comparing it to the libraries listed below

• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆38Updated 3 years ago
• dawsonjon / Chips-Demo
  Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.
  ☆16Updated 7 years ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆23Updated 4 years ago
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 12 years ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 10 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆32Updated 3 months ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• nandland / UART
  UART in Verilog and VHDL
  ☆11Updated 2 years ago
• abdelazeem201 / ASIC-Implementation-UART
  This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…
  ☆12Updated 3 years ago
• nandland / memory
  Single Port RAM, Dual Port RAM, FIFO
  ☆24Updated 3 years ago
• freecores / reed_solomon_decoder
  Reed Solomon Decoder (204,188)
  ☆12Updated 10 years ago
• vladniculescu / High-Speed-FPGA-based-Data-Acquisition-System-100MSPS
  ☆18Updated last year
• www-asics-ws / wb_conmax
  WISHBONE Interconnect
  ☆11Updated 7 years ago
• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆13Updated 7 months ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 5 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆30Updated 3 years ago
• amiq-consulting / physical_coding_library
  ☆18Updated 8 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆44Updated 9 years ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆41Updated 5 years ago
• mcci-catena / catena-riscv32-fpga
  RISC-V 32-bit core for MCCI Catena 4710
  ☆10Updated 5 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 4 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆60Updated 2 years ago
• GOOD-Stuff / FPGA-SPI-Flash
  Various projects of SPI loader module for xilinx fpga
  ☆30Updated 4 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆36Updated 3 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆35Updated 4 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆40Updated 7 years ago
• r09g / iadc
  12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm
  ☆18Updated 2 years ago