Alternatives and similar repositories for Verilog-Spectrum-Analyzer

Users that are interested in Verilog-Spectrum-Analyzer are comparing it to the libraries listed below

• abdelazeem201 / SoC-Implementation-of-OpenMSP430-Microcontroller
  The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…
  ☆15Updated 3 years ago
• abdelazeem201 / ASIC-Implementation-UART
  This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…
  ☆14Updated 3 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆17Updated 4 years ago
• CoreyChen922 / sata_2_host_controller
  Sata 2 Host Controller for FPGA implementation
  ☆18Updated 7 years ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆23Updated last year
• wnew / hdl_library
  A library of verilog and vhdl modules
  ☆15Updated 6 years ago
• www-asics-ws / wb_conmax
  WISHBONE Interconnect
  ☆11Updated 7 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆27Updated last week
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆40Updated 7 years ago
• geddy11 / netwiz
  Network protocol libraries for VHDL test benches
  ☆12Updated 3 months ago
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 13 years ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆23Updated 4 years ago
• maazm007 / 100Daysof_RTL
  The Repository contains the code of various Digital Circuits
  ☆11Updated 2 years ago
• r09g / iadc
  12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm
  ☆19Updated 2 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 11 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆58Updated 5 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆26Updated 4 years ago
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆43Updated 3 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆28Updated last year
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 11 years ago
• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆13Updated 3 weeks ago
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆22Updated 7 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆39Updated 4 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated 10 months ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆28Updated last year
• taneroksuz / cpu-medium
  6-stage in-order dual-issue superscalar risc-v cpu with floating point unit
  ☆13Updated 3 weeks ago
• proppy / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆8Updated last year