Alternatives and similar repositories for virtio-fpga-bridge

Users that are interested in virtio-fpga-bridge are comparing it to the libraries listed below

• RSPwFPGAs / virtio-fpga
  A platform for emulating Virtio devices with FPGAs
  ☆26Updated 4 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆48Updated 4 years ago
• tymonx / virtio
  Virtio implementation in SystemVerilog
  ☆47Updated 7 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• NetTLP / adapter
  An FPGA-based NetTLP adapter
  ☆27Updated 5 years ago
• shengwenliang / fpga-nvme-controller
  Chisel NVMe controller
  ☆21Updated 2 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆101Updated this week
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆39Updated 2 years ago
• NetTLP / libtlp
  A library for PCIe Transaction Layer
  ☆59Updated 3 years ago
• Xilinx / open-nic-driver
  AMD OpenNIC driver includes the Linux kernel driver
  ☆67Updated 7 months ago
• UofT-HPRC / fpga-bpf
  A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark
  ☆49Updated 4 years ago
• pcie-bench / pciebench-netfpga
  pcie-bench code for NetFPGA/VCU709 cards
  ☆37Updated 7 years ago
• slaclab / axi-pcie-core
  ☆21Updated last week
• Xilinx / pcie-model
  PCI Express controller model
  ☆59Updated 2 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆54Updated 5 years ago
• Xilinx / open-nic-shell
  AMD OpenNIC Shell includes the HDL source files
  ☆118Updated 7 months ago
• intel / pfr-wilson-city
  ☆24Updated 10 months ago
• chipsalliance / tilelink
  ☆32Updated 7 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆69Updated last year
• yu-zou / DirectNVM
  An open-source RTL NVMe controller IP for Xilinx FPGA.
  ☆53Updated 4 years ago
• luinaudt / deparser
  ☆16Updated 3 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• fpgasystems / davos
  Distributed Accelerator OS
  ☆63Updated 3 years ago
• texane / vpcie
  implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture
  ☆104Updated 7 years ago
• FPGA-Networking / HyperParser
  ☆35Updated 3 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆42Updated 6 months ago
• Pufferfish / tlm-of-a-pcie-rootcomplex-systemc
  A transaction level model of a PCI express root complex implemented in systemc
  ☆22Updated 11 years ago
• maswx / vu13p_corundum
  corundum work on vu13p
  ☆19Updated last year