lowRISC / ariane-ethernetLinks
open-source Ethenet media access controller for Ariane on Genesys-2
☆19Updated 6 years ago
Alternatives and similar repositories for ariane-ethernet
Users that are interested in ariane-ethernet are comparing it to the libraries listed below
Sorting:
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- General Purpose AXI Direct Memory Access☆59Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year
- A simple DDR3 memory controller☆60Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆78Updated 4 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆66Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆176Updated 10 months ago
- UART -> AXI Bridge☆63Updated 4 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆70Updated 4 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 9 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆61Updated last week
- Control and status register code generator toolchain☆147Updated this week
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆112Updated 4 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 3 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆140Updated last week
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆49Updated 4 years ago
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆22Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- Introductory course into static timing analysis (STA).☆97Updated 3 months ago
- ☆98Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated 2 months ago
- This is the repository for the IEEE version of the book☆71Updated 5 years ago
- ☆166Updated 3 years ago
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago