lowRISC / ariane-ethernet
open-source Ethenet media access controller for Ariane on Genesys-2
☆18Updated 5 years ago
Alternatives and similar repositories for ariane-ethernet:
Users that are interested in ariane-ethernet are comparing it to the libraries listed below
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆58Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆73Updated 2 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆16Updated 11 months ago
- UART models for cocotb☆27Updated 2 years ago
- ☆25Updated 3 years ago
- A demo system for Ibex including debug support and some peripherals☆63Updated 2 weeks ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆94Updated last month
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆60Updated last week
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- Python Tool for UVM Testbench Generation☆52Updated 11 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆50Updated 7 months ago
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆102Updated 3 years ago
- Ethernet interface modules for Cocotb☆63Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 2 months ago
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆15Updated last year
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆53Updated last year
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- A compact, configurable RISC-V core☆11Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- An example Python-based MDV testbench for apbi2c core☆30Updated 8 months ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆42Updated 11 months ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆56Updated 2 years ago
- Static Timing Analysis Full Course☆52Updated 2 years ago