Alternatives and similar repositories for nvme-pcie-to-fabrics-proxy:

Users that are interested in nvme-pcie-to-fabrics-proxy are comparing it to the libraries listed below

• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆44Updated 3 years ago
• ryuz / jelly
  Original FPGA platform
  ☆54Updated last week
• vengineer-systemverilog / All-of-SystemVerilog
  みんなのSystemVerilog
  ☆19Updated 2 years ago
• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 4 years ago
• pezy-computing / pzbcm
  Basic Common Modules
  ☆36Updated last month
• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆101Updated 2 years ago
• cpuex2019-yokyo / core
  RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
  ☆13Updated 4 years ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆102Updated 2 months ago
• tmatsuya / wiki
  ☆36Updated 7 years ago
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆35Updated 4 months ago
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆30Updated 6 months ago
• ciniml / fpga_samples
  FPGA samples
  ☆23Updated last month
• diningyo / dirv
  This is my first trial project for designing RISC-V in Chisel
  ☆17Updated 8 months ago
• MakeLSI / OpenRule1um
  Open design rule (1um)
  ☆18Updated 2 years ago
• nlsynth / iroha
  Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
  ☆35Updated 3 years ago
• horie-t / homemade-riscv
  『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
  ☆13Updated 5 years ago
• PyHDI / PyCoRAM
  Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
  ☆52Updated 8 years ago
• ghz-ws / fpga_dsp
  DSP by FPGA
  ☆12Updated last year
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆148Updated 2 months ago
• onikiri / onikiri2
  ☆38Updated 4 months ago
• synthesijer / synthesijer
  ☆52Updated 5 months ago
• msyksphinz-self / swimmer_riscv
  Instruction set simulator for RISC-V
  ☆52Updated 4 years ago
• aquaxis / synverll
  ☆14Updated 8 years ago
• RuSys / Verugent
  Verilog generation tool written in Rust
  ☆57Updated last year
• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆20Updated 2 years ago
• ikwzm / ZynqMP-ACP-Adapter
  Xilinx ZynqMP AXI-ACP Adapter
  ☆15Updated 2 years ago
• miyo / learning_fpga
  ☆9Updated 4 years ago
• ciniml / seccamp_riscv_cpu
  セキュリティ・キャンプ 2022-2024 RISC-V CPU自作ゼミ 資料置き場
  ☆37Updated last month
• i4kimura / chisel-minicpu
  ☆14Updated 5 years ago