sora / ovs-hwLinks
An open source hardware engine for Open vSwitch on FPGA
☆26Updated 13 years ago
Alternatives and similar repositories for ovs-hw
Users that are interested in ovs-hw are comparing it to the libraries listed below
Sorting:
- This repo contains the Limago code☆90Updated 7 months ago
- AMD OpenNIC Shell includes the HDL source files☆134Updated 11 months ago
- NetFPGA public repository☆182Updated 5 years ago
- ☆48Updated 6 years ago
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆134Updated 4 years ago
- Distributed Accelerator OS☆63Updated 3 years ago
- Ethernet switch implementation written in Verilog☆54Updated 2 years ago
- FAST☆38Updated 9 years ago
- Virtio implementation in SystemVerilog☆48Updated 7 years ago
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 3 months ago
- Network packet parser generator☆53Updated 5 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆40Updated 2 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆46Updated 2 years ago
- AMD OpenNIC driver includes the Linux kernel driver☆69Updated 11 months ago
- Verilog network module. Models network traffic from pcap to AXI-Stream☆22Updated 4 years ago
- NetFPGA-SUME public repository☆113Updated 10 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆53Updated 2 years ago
- Framework for FPGA-accelerated Middlebox Development☆48Updated 2 years ago
- P4-14/16 Bluespec Compiler☆89Updated 7 years ago
- Connectal is a framework for software-driven hardware development.☆176Updated 2 years ago
- ☆53Updated last year
- ESnet SmartNIC hardware design repository.☆59Updated 3 weeks ago
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- DPDK Drivers for AMD OpenNIC☆27Updated 2 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆69Updated 8 years ago
- ☆26Updated 4 years ago
- Network Development Kit (NDK) for FPGA cards with example application☆68Updated last week
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆77Updated 6 years ago
- Simple hash table on Verilog (SystemVerilog)☆50Updated 9 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆51Updated 4 years ago