Alternatives and similar repositories for riscv-vectorized-benchmark-suite

Users that are interested in riscv-vectorized-benchmark-suite are comparing it to the libraries listed below

• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆36Updated 3 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆127Updated last year
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆143Updated 2 weeks ago
• masc-ucsc / esesc
  ESESC: A Fast Multicore Simulator
  ☆140Updated 3 months ago
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆56Updated 4 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆100Updated 3 weeks ago
• VerticalResearchGroup / microbench
  Extremely Simple Microbenchmarks
  ☆39Updated 7 years ago
• UT-LCA / Scalability-Phase-Simpoint-of-SPEC-CPU2017
  ☆33Updated 5 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆42Updated 2 years ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆154Updated 3 years ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆33Updated 2 years ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• arm-university / arm-gem5-rsk
  Official repository of the Arm Research Starter Kit on System Modeling using gem5
  ☆118Updated 7 months ago
• aakahlow / gem5Valid_Haswell
  ☆21Updated 6 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆100Updated 3 months ago
• rivosinc / veclibm
  Vector math library using RISC-V vector ISA via C intrinsic
  ☆24Updated 3 weeks ago
• cry-daniel / Computer-Architecture-Learning
  ☆64Updated 3 years ago
• riscv-admin / riscv-ovpsim
  ☆62Updated 5 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆55Updated 3 weeks ago
• ccelio / Speckle
  A wrapper for the SPEC CPU2006 benchmark suite.
  ☆91Updated 4 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 3 years ago
• 2Bor2C / tage
  Implementation of TAGE Branch Predictor - currently considered state of the art
  ☆52Updated 11 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆163Updated 2 years ago
• bring-your-own-core / byoc
  The OpenPiton Platform
  ☆28Updated 2 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆109Updated last year
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆101Updated this week
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆46Updated last week
• ISRC-CAS / c910-llvm
  平头哥玄铁C910的LLVM工具链支持，由PLCT实验室提供，非官方版本
  ☆76Updated 4 years ago
• riscv / riscv-bfloat16
  ☆38Updated last year
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆151Updated this week