freecores / novaLinks
H.264/AVC Baseline Decoder
☆15Updated 11 years ago
Alternatives and similar repositories for nova
Users that are interested in nova are comparing it to the libraries listed below
Sorting:
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 9 years ago
- Altera Cyclone IV FPGA project for the PCIe LimeSDR board☆41Updated 3 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 5 years ago
- PCIe DMA Subsystem based on Xilinx XAPP1171☆49Updated 2 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆69Updated 8 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- SDRAM controller for MIPSfpga+ system☆24Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020☆56Updated 8 years ago
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆60Updated 6 months ago
- Extensible FPGA control platform☆61Updated 2 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/x393☆40Updated 2 years ago
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- Eclipse based IDE for RISC-V bare metal software development.☆20Updated 6 years ago
- Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces☆35Updated last year
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- IP Cores that can be used within Vivado☆26Updated 4 years ago
- VHDL PCIe Transceiver☆31Updated 5 years ago
- USB Full Speed PHY☆48Updated 5 years ago
- Small projects intended to run on the Digilent Zybo development board, utilizing PetaLinux on the Zynq's ARM processor.☆23Updated 9 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- Revision Control Labs and Materials☆25Updated 7 years ago
- MIPSfpga+ allows loading programs via UART and has a switchable clock☆111Updated 6 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 13 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆86Updated 2 years ago
- An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.☆50Updated 12 years ago