H.264/AVC Baseline Decoder
☆16Jul 17, 2014Updated 12 years ago
Alternatives and similar repositories for nova
Users that are interested in nova are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆25Mar 19, 2021Updated 5 years ago
- Bluespec H.264 Decoder☆13Jul 17, 2014Updated 12 years ago
- UART 16550 core☆45Jul 17, 2014Updated 12 years ago
- Cycle accurate MC6502 compatible processor in Verilog.☆16Oct 11, 2021Updated 5 years ago
- openMSP430 CPU core (from OpenCores)☆22Oct 14, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Embedded 32-bit RISC uProcessor with SDRAM Controller☆26Sep 2, 2021Updated 5 years ago
- Multi-threaded 32-bit embedded core family.☆24Jul 9, 2012Updated 14 years ago
- H264视频解码verilog实现☆92Aug 11, 2017Updated 9 years ago
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 12 years ago
- Design and Verification of a Complete Application Specific Integrated Circuit☆12Nov 21, 2016Updated 9 years ago
- Sound synthetizer with an fpga☆11Mar 14, 2015Updated 11 years ago
- Just experimenting with Open Source SoCs on my Altera dev kit.☆12Feb 10, 2012Updated 14 years ago
- a MIPS-based embedded system on FPGA☆10Mar 10, 2017Updated 9 years ago
- OFDM baseband processing systerm based on IEEE 802.11a☆13Aug 3, 2020Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Open source implementation of a x86 processor http://zet.aluzina.org☆11Mar 17, 2014Updated 12 years ago
- Amber ARM-compatible core☆18Jul 17, 2014Updated 12 years ago
- Reed Solomon Decoder (204,188)☆12Jul 17, 2014Updated 12 years ago
- Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm☆17Mar 3, 2018Updated 8 years ago
- Silicon-proven INT8 systolic NPU (8×8 MAC array) taped out on SkyWater 130nm via LibreLane. Features a custom 32-bit ISA, UART–APB host i…☆20May 24, 2026Updated 5 months ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- Basic scripts for Synopsys Design Compiler and Synopsys IC Compiler☆10Mar 31, 2018Updated 8 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- OpenGL-like graphics pipeline on a Xilinx FPGA☆35Dec 14, 2010Updated 15 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A MIPS32 System-on-Chip for the DE0-Nano FPGA☆12Sep 1, 2014Updated 12 years ago
- turbo 8051☆31Aug 30, 2017Updated 9 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆42Jan 12, 2016Updated 10 years ago
- Port of Amber ARM Core project to Marsohod2 platform☆13Dec 4, 2019Updated 6 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆35Sep 17, 2019Updated 7 years ago
- 18-545 project: ARM-like SoC☆15Dec 5, 2010Updated 15 years ago
- DEPRECATED see https://github.com/julbouln/musicboard for updated version STM32F746g Discovery board SF2 polyphonic MIDI synthesizer☆21Jun 12, 2020Updated 6 years ago
- Matrix Multiplication in Hardware☆17Jun 3, 2020Updated 6 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆23Jan 31, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- An rtsp and rtp server made for one of my classes in university.☆10May 11, 2012Updated 14 years ago
- 使用Verilog设计的带四舍五入功能的浮点加法器☆22Dec 19, 2011Updated 14 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- Super scalar Processor design☆21Sep 7, 2014Updated 12 years ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- AES☆16Oct 4, 2022Updated 4 years ago
- Using tuntap to simulate router port, implement software router and related network functions with C.☆16Sep 27, 2020Updated 6 years ago