verilog_instance.vim: create instantiation of ports from port declaration
☆31Mar 13, 2023Updated 3 years ago
Alternatives and similar repositories for vim-verilog-instance
Users that are interested in vim-verilog-instance are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Edit SystemVerilog files (and UVM files) in Vim/gVim☆30Mar 8, 2024Updated 2 years ago
- Verilog/SystemVerilog Syntax and Omni-completion☆418Oct 13, 2024Updated last year
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 7 months ago
- A Verilog IEEE 1364-2005 language server written in Nim.☆15Aug 25, 2022Updated 3 years ago
- ☆135Nov 17, 2025Updated 7 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- SystemVerilog & Verilog Module I/O parser and printer☆26Jul 1, 2026Updated last week
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆65Sep 25, 2023Updated 2 years ago
- Graphviz dot to Verilog Finite State Machine (FSM) generator written in Python☆15Feb 3, 2021Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆32Jul 12, 2024Updated last year
- SystemVerilog vim scripts☆68Jan 25, 2023Updated 3 years ago
- A Tcl-Library for scripted HDL generation☆18Apr 30, 2024Updated 2 years ago
- AXI X-Bar☆19Apr 8, 2020Updated 6 years ago
- Generate inteligent customisable markdown TOC with affordances for emojis and relative file paths.☆17May 28, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Repurposing existing HDL tools to help writing better code☆224Jun 21, 2026Updated 2 weeks ago
- Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3☆37Aug 6, 2013Updated 12 years ago
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆38Jun 16, 2026Updated 3 weeks ago
- SystemVerilog Logger☆19Apr 6, 2026Updated 3 months ago
- tools regarding on analog modeling, validation, and generation☆24Apr 11, 2023Updated 3 years ago
- Medium Access Control layer of 802.15.4☆14Nov 14, 2014Updated 11 years ago
- Improve startup time for Neovim☆12Dec 27, 2021Updated 4 years ago
- Simple template-based UVM code generator☆30Apr 15, 2026Updated 2 months ago
- ☆20Nov 16, 2014Updated 11 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆12Jan 17, 2024Updated 2 years ago
- VCD file viewer for Neovim☆15Feb 20, 2022Updated 4 years ago
- A tool for checking tool output inspired by LLVM's FileCheck☆13Aug 29, 2025Updated 10 months ago
- Simple parser for extracting VHDL documentation☆74Jul 12, 2024Updated last year
- Log file scanner used with EDA tools to classify errors and warnings☆13Nov 14, 2022Updated 3 years ago
- SystemVerilog grammar for tree-sitter☆119Nov 11, 2024Updated last year
- PCI Express ® Base Specification Revision 3.0☆13May 23, 2018Updated 8 years ago
- ☆67Jul 25, 2020Updated 5 years ago
- ☆30Feb 4, 2021Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago
- ☆12May 20, 2021Updated 5 years ago
- A minimum configuration for Neovim targeting SystemVerilog that provides configuration for plugin management, a language server, tree-sit…☆28May 27, 2024Updated 2 years ago
- This repository tracks the changes the the "Unix Timesharing System" paper written by Dennis Ritchie and Ken Thompson.☆11Oct 6, 2018Updated 7 years ago
- QQSPI Pmod-compatible 32MB PSRAM module☆16Sep 14, 2023Updated 2 years ago
- ☆12Sep 26, 2021Updated 4 years ago
- Multiview variant of Pointpillars. Contains Pytorch reimplementation of Pillar-od.☆14Jan 15, 2021Updated 5 years ago