Alternatives and similar repositories for vim-verilog-instance

Users that are interested in vim-verilog-instance are comparing it to the libraries listed below

• jmcneal / verilog-support
  Edit SystemVerilog files (and UVM files) in Vim/gVim
  ☆29Updated last year
• zhuzhzh / verilog_emacsauto.vim
  verilog filetype plugin to enable emacs verilog-mode autos
  ☆25Updated 3 years ago
• nachumk / systemverilog.vim
  SystemVerilog vim scripts
  ☆66Updated 2 years ago
• antoinemadec / uvm_code_gen
  Simple template-based UVM code generator
  ☆26Updated 2 years ago
• WeiChungWu / vim-SystemVerilog
  SystemVerilog syntax highlight/indent support in vim
  ☆50Updated 10 months ago
• jimmysitu / vtags
  Verdi like, verilog code signal trace and show hierarchy script
  ☆19Updated 5 years ago
• imc-trading / svlangserver
  ☆109Updated 11 months ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆25Updated 5 years ago
• uvmdebug / uvm_debug
  UVM interactive debug library
  ☆32Updated 8 years ago
• vim-scripts / verilog_emacsauto.vim
  verilog filetype plugin to enable emacs verilog-mode autos
  ☆17Updated 3 years ago
• kaushalmodi / custom_uvm_report_server
  Customized UVM Report Server
  ☆40Updated 5 years ago
• funningboy / vim
  UVM/systemverilog/verilog/python VIM IDE
  ☆16Updated 11 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆60Updated 4 years ago
• taichi-ishitani / tue
  Useful UVM extensions
  ☆22Updated 10 months ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 6 years ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆100Updated 6 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆52Updated 11 months ago
• freecores / robust_axi_fabric
  Generic AXI interconnect fabric
  ☆13Updated 10 years ago
• zhajio1988 / my_vimrc
  Jude's vimrc for DV work(fine tuning for SV/UVM)
  ☆18Updated last year
• hjking / uvm_gen
  UVM Generator
  ☆45Updated last year
• amiq-consulting / yamm
  YAMM package repository
  ☆26Updated 2 years ago
• chipsalliance / homebrew-verible
  ☆20Updated 2 months ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated this week
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆98Updated last year
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆28Updated 2 years ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆58Updated 4 months ago
• chiggs / UVM
  Mirror of the Universal Verification Methodology from sourceforge
  ☆33Updated 10 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆58Updated 4 years ago
• go2uvm / sva_traces
  Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors
  ☆10Updated 8 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆48Updated 4 months ago