antoinemadec / vim-verilog-instance
verilog_instance.vim: create instantiation of ports from port declaration
☆27Updated last year
Alternatives and similar repositories for vim-verilog-instance:
Users that are interested in vim-verilog-instance are comparing it to the libraries listed below
- Edit SystemVerilog files (and UVM files) in Vim/gVim☆27Updated 10 months ago
- verilog filetype plugin to enable emacs verilog-mode autos☆24Updated 2 years ago
- SystemVerilog vim scripts☆65Updated last year
- SystemVerilog syntax highlight/indent support in vim☆50Updated 6 months ago
- ☆104Updated 7 months ago
- Simple template-based UVM code generator☆23Updated 2 years ago
- Verdi like, verilog code signal trace and show hierarchy script☆19Updated 5 years ago
- verilog filetype plugin to enable emacs verilog-mode autos☆17Updated 2 years ago
- Generate UVM testbench framework template files with Python 3☆25Updated 5 years ago
- UVM interactive debug library☆32Updated 7 years ago
- ☆18Updated 3 months ago
- UVM Generator☆43Updated 8 months ago
- This is the repository for the IEEE version of the book☆53Updated 4 years ago
- ☆60Updated 4 years ago
- Rewrite of tree-sitter-verilog☆16Updated last week
- SystemVerilog grammar for tree-sitter☆95Updated 2 months ago
- Doxygen with verilog support☆37Updated 5 years ago
- SystemVerilog modules and classes commonly used for verification☆45Updated last week
- Generate UVM register model from compiled SystemRDL input☆51Updated 4 months ago
- Customized UVM Report Server☆37Updated 4 years ago
- ideas and eda software for vlsi design☆48Updated 2 weeks ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆45Updated 4 years ago
- Jude's vimrc for DV work(fine tuning for SV/UVM)☆18Updated 10 months ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆88Updated last year
- A Verilog IEEE 1364-2005 language server written in Nim.☆15Updated 2 years ago
- UVM verification kits which uses YASA as simulation script☆13Updated 5 years ago
- Altera Advanced Synthesis Cookbook 11.0☆96Updated last year
- UVM and System Verilog Manuals☆38Updated 5 years ago
- UVM agents☆76Updated 7 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆125Updated 11 months ago