Alternatives and similar repositories for vim-verilog-instance:

Users that are interested in vim-verilog-instance are comparing it to the libraries listed below

• jmcneal / verilog-support
  Edit SystemVerilog files (and UVM files) in Vim/gVim
  ☆29Updated last year
• zhuzhzh / verilog_emacsauto.vim
  verilog filetype plugin to enable emacs verilog-mode autos
  ☆25Updated 3 years ago
• nachumk / systemverilog.vim
  SystemVerilog vim scripts
  ☆65Updated 2 years ago
• WeiChungWu / vim-SystemVerilog
  SystemVerilog syntax highlight/indent support in vim
  ☆50Updated 9 months ago
• jimmysitu / vtags
  Verdi like, verilog code signal trace and show hierarchy script
  ☆19Updated 5 years ago
• imc-trading / svlangserver
  ☆109Updated 11 months ago
• antoinemadec / uvm_code_gen
  Simple template-based UVM code generator
  ☆26Updated 2 years ago
• vim-scripts / verilog_emacsauto.vim
  verilog filetype plugin to enable emacs verilog-mode autos
  ☆17Updated 3 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆130Updated last year
• zion-group / VerilogCodingStyle
  ☆63Updated 4 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated this week
• uvmdebug / uvm_debug
  UVM interactive debug library
  ☆32Updated 7 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆96Updated last year
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆99Updated 5 months ago
• hjking / uvm_gen
  UVM Generator
  ☆45Updated 11 months ago
• suzizecat / slang-lsp-tools
  Tools based upon slang for language server purpose
  ☆12Updated last month
• kaushalmodi / custom_uvm_report_server
  Customized UVM Report Server
  ☆40Updated 5 years ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆103Updated 2 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆47Updated 3 months ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆25Updated 5 years ago
• sach / System-Verilog-Packet-Library
  System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
  ☆73Updated 6 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆58Updated 4 years ago
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆207Updated 10 months ago
• taichi-ishitani / tue
  Useful UVM extensions
  ☆22Updated 9 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆57Updated 3 months ago
• zhajio1988 / my_vimrc
  Jude's vimrc for DV work(fine tuning for SV/UVM)
  ☆18Updated last year
• n-kremeris / verilator_basics
  ☆61Updated 2 years ago
• accellera / uvm
  ☆49Updated 8 years ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 6 years ago
• amiq-consulting / yamm
  YAMM package repository
  ☆26Updated 2 years ago