A simple 5-stage Pipeline RISC-V core
☆19Jun 8, 2021Updated 5 years ago
Alternatives and similar repositories for NF5
Users that are interested in NF5 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- >>> 异常中断 + 虚存页表 + 分支预测 + TLB + Cache + Flash + VGA + uCore☆20Nov 17, 2023Updated 2 years ago
- This is my graduation project, a simple processor soft core, which implements RV32I ISA.☆17May 23, 2019Updated 7 years ago
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 8 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- RV32I Single Cycle Processor (CPU)☆12Nov 14, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Source of Feitian OpenSK USB Dongle help docs.☆11Jul 5, 2022Updated 4 years ago
- ☆14Jul 17, 2020Updated 6 years ago
- Mirror only see https://gitlab.rtems.org/rtems/docs/rtems-docs/☆11Updated this week
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Nov 27, 2022Updated 3 years ago
- Open SoC Debug Hardware Reference Implementation☆16Jul 15, 2019Updated 7 years ago
- Scripts to recover (accidentally) deleted files from ext3 partitions☆13Aug 16, 2017Updated 9 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆19Dec 5, 2022Updated 3 years ago
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆53Jul 21, 2022Updated 4 years ago
- EC499: Major Project☆11Jun 25, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆10Nov 12, 2019Updated 6 years ago
- In this project, the simulation of simple digital hearing aid was developed using MATLAB programming language. The implementation of this…☆10Nov 11, 2021Updated 4 years ago
- Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction☆12Apr 21, 2022Updated 4 years ago
- A pipelined RISC-V processor☆65Dec 1, 2023Updated 2 years ago
- A Kubernetes cluster to learn Kubernetes. It includes Argo CD, Grafana, Prometheus, Loki, Tempo, Phlare and VictoriaMetrics.☆11Updated this week
- WolkGateway bridges communication between WolkAbout IoT platform and multiple devices connected to it☆12Nov 27, 2024Updated last year
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- archlinux的loongarch64-bootstrap版本(为了可以迅速迭代跟进上游工具链,archlinux-loongarch64-bootstrap只滚动base-devel包组),基础工具链源码取自上游开源社区最新状态的linux/gcc/glibc/bin…☆10Jun 8, 2022Updated 4 years ago
- Open-Source EDA workshop for RISC-V community☆12Jul 27, 2022Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆12Dec 20, 2013Updated 12 years ago
- SRAM macros created for the GF180MCU provided by GlobalFoundries.☆20Apr 10, 2023Updated 3 years ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- Cryptography Library using hardware-accelerated ARM CryptoCell CC310 on nRF52-based Bluefruit☆13Oct 14, 2023Updated 2 years ago
- SoC for CQU Dual Issue Machine☆12Sep 20, 2022Updated 3 years ago
- CKLink_Lite☆12Oct 18, 2021Updated 4 years ago
- ☆15Jan 6, 2020Updated 6 years ago
- EVE Online Visual Intel Tool☆11Apr 18, 2018Updated 8 years ago
- [創造情報院試プログラミング] 過去問の解答☆11Jul 6, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Communication-Minimizing 2D Convolution in GPU Registers☆30Sep 21, 2013Updated 12 years ago
- A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga)☆10Apr 20, 2026Updated 3 months ago
- ☆13Apr 22, 2026Updated 3 months ago
- 支持CMSIS-DAP v2接口协议,支持ARM、RISCV、ESP32等目标芯片,详见Wiki及release☆55Updated this week
- This repository describes two frameworks which can be used for pre-Silicon power side-channel analysis of digital circuit designs (i.e., …☆16Feb 16, 2022Updated 4 years ago
- 32-bit RISC-V based processor with memory controler☆16Sep 2, 2022Updated 3 years ago
- ACI-GetStarted☆11Aug 7, 2026Updated last week