NSCSCC “龙芯杯” 2024 个人赛 LoongArch 赛道三等奖
☆20Aug 17, 2024Updated last year
Alternatives and similar repositories for xucpu
Users that are interested in xucpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 2024年第八届龙芯杯 LA 个人赛二等奖参赛作品☆30Aug 20, 2024Updated last year
- 基于LoongArch32/MIPS32指令集的七级流水线CPU。2023年龙芯杯（NSCSCC）个人赛参赛作品。☆43Apr 24, 2025Updated last year
- CPU敏捷开发框架（龙芯杯2024）☆28Sep 6, 2024Updated last year
- CPU source code for NSCSCC 2023☆14Aug 26, 2023Updated 2 years ago
- 本仓库用于开源分享本人的第九届龙芯杯个人赛参赛作品☆16Aug 27, 2025Updated 11 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- 2020龙芯杯个人赛 简易双发射60M（含ibuffer）☆46Aug 24, 2020Updated 5 years ago
- 龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）☆65Mar 6, 2024Updated 2 years ago
- 龙芯杯2021个人赛决赛最终代码☆11Sep 1, 2021Updated 4 years ago
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品☆26Sep 14, 2024Updated last year
- 2022年龙芯杯个人赛 单发射110M（含icache）☆54Aug 22, 2022Updated 3 years ago
- 2022龙芯杯个人赛三等奖作品☆14Oct 11, 2023Updated 2 years ago
- 龙芯杯21个人赛作品☆36Sep 15, 2021Updated 4 years ago
- ☆31Jul 9, 2026Updated 2 weeks ago
- some notes for opensource llm technical reorts☆20Mar 6, 2026Updated 4 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 清华大学“荷塘雨课堂”助手，包含自动签到、答题等功能。☆24Dec 4, 2025Updated 7 months ago
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- ☆18Jul 2, 2026Updated 3 weeks ago
- ☆18Jul 9, 2026Updated 2 weeks ago
- Nemu抄PA的给个star好嘛，看代码的时候可以根据pa切换分支，默认是pa2☆17Mar 28, 2021Updated 5 years ago
- 《CPU设计实战》汪文祥 全书代码 完整版 Loongarch版☆18May 14, 2026Updated 2 months ago
- Web front for EESAST☆11Updated this week
- This is my graduation project, a simple processor soft core, which implements RV32I ISA.☆17May 23, 2019Updated 7 years ago
- ☆16May 28, 2026Updated 2 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆96Aug 29, 2023Updated 2 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Jul 23, 2020Updated 6 years ago
- ☆23Oct 22, 2023Updated 2 years ago
- A 32-bit 5-stage RISC-V pipeline processor core with traps, S privilege mode, virtual memory, cache, branch prediction and TLB. Powered b…☆15Feb 14, 2024Updated 2 years ago
- An eye-friendly dark theme for Typora.☆12Apr 22, 2022Updated 4 years ago
- BUAA Compiler Course Project 2023 by Toby Shi.☆13Aug 20, 2024Updated last year
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14May 26, 2026Updated 2 months ago
- Chongqing University 2020 NSCSCC☆29Oct 13, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A small and simple rv32i core written in Verilog☆18Jul 29, 2022Updated 3 years ago
- ☆19May 1, 2023Updated 3 years ago
- Code for papers Optimal Reservoir Operations using Long Short-Term Memory Network and Bi-directional Storage Capacity and Elevation Level…☆17Sep 10, 2021Updated 4 years ago
- Convert Verilog to a Hardcaml design☆22Jul 10, 2026Updated 2 weeks ago
- OpenReLife is an OpenSource, AI powered alternative to Rewind.ai, seeking for a great UX and a delightful UI☆23Jul 10, 2026Updated 2 weeks ago
- SaTML'23 paper "Backdoor Attacks on Time Series: A Generative Approach" by Yujing Jiang, Xingjun Ma, Sarah Monazam Erfani, and James Bail…☆21Feb 5, 2023Updated 3 years ago
- 16QAM modulation and demodulation by Verilog☆20Jan 4, 2021Updated 5 years ago