VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (RL). It provides a generic Gym environment implementation for building cocotb-based testbenches for verifying any hardware design.
☆31Oct 5, 2022Updated 3 years ago
Alternatives and similar repositories for VeRLPy
Users that are interested in VeRLPy are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- LLM4DV☆24Sep 30, 2024Updated last year
- Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"☆15Sep 12, 2022Updated 3 years ago
- RISC-V Formal in Chisel☆13Apr 9, 2024Updated 2 years ago
- Combination of Analog Circuit Sizing and DL.☆18Mar 24, 2023Updated 3 years ago
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆12Mar 31, 2023Updated 3 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- ☆10Jan 15, 2023Updated 3 years ago
- A Formal Verification Framework for Chisel☆21Apr 9, 2024Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Nov 12, 2025Updated 8 months ago
- Verilog implementation of MC68851 Memory Management Unit☆14Feb 26, 2018Updated 8 years ago
- Complete simulation of IEEE 754 fixed and floating point specification to any precision☆13Aug 26, 2020Updated 5 years ago
- GNN-RE datasets for circuit recognition☆59May 16, 2023Updated 3 years ago
- Open-Source Framework for Co-Emulation☆13Feb 12, 2021Updated 5 years ago
- Spiking Neural Network Accelerator☆15May 18, 2022Updated 4 years ago
- CMurphi mirror: http://mclab.di.uniroma1.it/site/index.php/software/18-cmurphi☆14Jan 22, 2016Updated 10 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- SystemVerilog (IEEE 1800-2017) Simulator☆61Updated this week
- CV32E40X Design-Verification environment☆16Jun 2, 2026Updated last month
- Simplifier of logical functions using Quine-McCluskey algorithm☆27Jun 24, 2018Updated 8 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆147Jul 5, 2026Updated 2 weeks ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Aug 7, 2023Updated 2 years ago
- ☆16Jan 7, 2023Updated 3 years ago
- Memory consistency model checking and test generation library.☆15Oct 14, 2016Updated 9 years ago
- ☆17Oct 2, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Branch predictor simulation, analysis, and Python compatibility for the 5th Championship Branch Prediction in 2016 (CBP-16)☆22Mar 9, 2023Updated 3 years ago
- A Barrel design of RV32I☆22Jul 30, 2023Updated 2 years ago
- Testing processors with Random Instruction Generation☆60Jan 13, 2026Updated 6 months ago
- ☆10Oct 15, 2021Updated 4 years ago
- ☆34Dec 16, 2021Updated 4 years ago
- Machine Generated Analog IC Layout☆291Apr 24, 2024Updated 2 years ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated last year
- Tools for working with circuits as graphs in python☆129Nov 17, 2023Updated 2 years ago
- ☆18Nov 9, 2022Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Research project from UCI's AICPS lab: using GNNs to enable hardware security and prevent hardware trojans☆10Mar 31, 2021Updated 5 years ago
- ☆15Sep 14, 2020Updated 5 years ago
- ☆15Feb 6, 2021Updated 5 years ago
- Host software for running SSITH processors on AWS F1 FPGAs☆20Jul 20, 2021Updated 5 years ago
- The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.☆48Jul 13, 2026Updated last week
- ☆21Nov 22, 2021Updated 4 years ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆20Jul 8, 2026Updated last week