aebeljs / VeRLPyLinks
VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (RL). It provides a generic Gym environment implementation for building cocotb-based testbenches for verifying any hardware design.
☆30Updated 3 years ago
Alternatives and similar repositories for VeRLPy
Users that are interested in VeRLPy are comparing it to the libraries listed below
Sorting:
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆95Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆34Updated 6 months ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆24Updated 6 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Updated 4 years ago
- This is a tutorial on standard digital design flow☆80Updated 4 years ago
- EDA physical synthesis optimization kit☆64Updated 2 years ago
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆134Updated last month
- ☆95Updated 5 months ago
- ☆110Updated last month
- Introductory course into static timing analysis (STA).☆99Updated 5 months ago
- Digital Standard Cells based SAR ADC☆14Updated 4 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆115Updated 5 years ago
- A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COrouti…☆21Updated last year
- Material for OpenROAD Tutorial at DAC 2020☆46Updated 3 years ago
- ☆14Updated 3 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆32Updated last week
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆53Updated 4 years ago
- Tools for working with circuits as graphs in python☆126Updated 2 years ago
- Verilog/SystemVerilog Guide☆75Updated last year
- Hardware Formal Verification☆16Updated 5 years ago
- ☆38Updated 6 months ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 3 years ago
- ☆32Updated 4 years ago
- Python wrapper for verilator model☆92Updated last year
- Running Python code in SystemVerilog☆71Updated 6 months ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated last month
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆49Updated 4 years ago