aebeljs / VeRLPy
VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (RL). It provides a generic Gym environment implementation for building cocotb-based testbenches for verifying any hardware design.
☆24Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for VeRLPy
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆73Updated 7 months ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆18Updated 5 years ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated 2 weeks ago
- EE 260 Winter 2017: Advanced VLSI Design☆58Updated 7 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆24Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)