Alternatives and similar repositories for VeRLPy

Users that are interested in VeRLPy are comparing it to the libraries listed below

• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆98Updated last year
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆24Updated 6 years ago
• NVlabs / CircuitOps
  ☆97Updated 7 months ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆35Updated 7 months ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆64Updated 2 years ago
• johnjohnlin / nicotb
  A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COrouti…
  ☆21Updated 2 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆99Updated 6 months ago
• A-T-Kristensen / simple-alu-uvm
  This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit
  ☆27Updated 7 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆33Updated last month
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆83Updated 4 years ago
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆126Updated 2 years ago
• hkust-zhiyao / NetTAG
  NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)
  ☆23Updated last month
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆60Updated 2 years ago
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆17Updated 5 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆32Updated 4 years ago
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆79Updated 2 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆57Updated 3 weeks ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆137Updated 2 weeks ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆28Updated 4 years ago
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆45Updated last year
• ABKGroup / PROBE3.0
  ☆50Updated last year
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated 2 months ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆92Updated last year
• openecos-projects / icsprout55-pdk
  55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
  ☆166Updated last month
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆51Updated 5 years ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• aolofsson / POSH
  ☆44Updated 6 years ago
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆54Updated last year
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆59Updated last week
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆68Updated 9 years ago