aebeljs / VeRLPyLinks
VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (RL). It provides a generic Gym environment implementation for building cocotb-based testbenches for verifying any hardware design.
☆30Updated 3 years ago
Alternatives and similar repositories for VeRLPy
Users that are interested in VeRLPy are comparing it to the libraries listed below
Sorting:
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆24Updated 6 years ago
- This is a tutorial on standard digital design flow☆83Updated 4 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆35Updated 8 months ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆27Updated 7 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆33Updated last month
- Complete tutorial code.☆23Updated last year
- EDA physical synthesis optimization kit☆64Updated 2 years ago
- A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COrouti…☆21Updated 2 years ago
- ideas and eda software for vlsi design☆51Updated this week
- ☆44Updated 6 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Updated 5 years ago
- Hardware Formal Verification☆17Updated 5 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆67Updated 9 years ago
- Material for OpenROAD Tutorial at DAC 2020☆46Updated 3 years ago
- ☆113Updated 2 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 5 years ago
- Introductory course into static timing analysis (STA).☆99Updated 7 months ago
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 4 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆10Updated 5 years ago
- Python wrapper for verilator model☆93Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆79Updated 2 months ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆26Updated 3 years ago
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- Digital Standard Cells based SAR ADC☆14Updated 4 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆32Updated 2 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆57Updated last month