aebeljs / VeRLPyLinks
VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (RL). It provides a generic Gym environment implementation for building cocotb-based testbenches for verifying any hardware design.
☆27Updated 2 years ago
Alternatives and similar repositories for VeRLPy
Users that are interested in VeRLPy are comparing it to the libraries listed below
Sorting:
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆85Updated last year
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated last month
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆23Updated 6 years ago
- ☆86Updated 3 weeks ago
- Python wrapper for verilator model☆86Updated last year
- EDA physical synthesis optimization kit☆59Updated last year
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- SystemVerilog RTL Linter for YoSys☆21Updated 7 months ago
- ☆13Updated 2 years ago
- Benchmarks for Approximate Circuit Synthesis☆16Updated 4 years ago
- ☆27Updated last week
- Project repo for the POSH on-chip network generator☆48Updated 4 months ago
- ideas and eda software for vlsi design☆50Updated 3 weeks ago
- IDEA project source files☆107Updated 8 months ago
- DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)☆114Updated 2 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆123Updated last month
- Introductory course into static timing analysis (STA).☆94Updated last week
- ☆31Updated 3 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆24Updated 6 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Updated 4 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆27Updated 5 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated this week
- An open-source benchmark for generating design RTL with natural language☆121Updated 8 months ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆58Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆29Updated last month
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 3 years ago
- Hardware Formal Verification☆15Updated 4 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆106Updated 4 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year