Alternatives and similar repositories for ReducedLUT

Users that are interested in ReducedLUT are comparing it to the libraries listed below

• MartaAndronic / NeuraLUT
  NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions
  ☆37Updated 3 months ago
• awai54st / Logic-Shrinkage
  ☆23Updated 2 years ago
• taneroksuz / mult-tree
  Wallace and Dadda tree multiplier generator in vhdl and verilog
  ☆12Updated 7 months ago
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆29Updated last year
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆40Updated 3 years ago
• pulp-platform / rbe
  Reconfigurable Binary Engine
  ☆17Updated 4 years ago
• shailja-thakur / AutoChip
  ☆30Updated 4 months ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆35Updated 5 months ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 3 years ago
• masc-ucsc / hdlagent
  LLM Agent for Hardware Description Language
  ☆19Updated last month
• wallento / riscv-python-model
  Python Model of the RISC-V ISA
  ☆51Updated 3 years ago
• ehw-fit / approx-fpgas
  Approximate arithmetic circuits for FPGAs
  ☆12Updated 5 years ago
• openhwgroup / cvw-arch-verif
  The purpose of the repo is to support CORE-V Wally architectural verification
  ☆13Updated this week
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆22Updated 3 years ago
• qleenju / PDPU
  PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
  ☆41Updated 2 years ago
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆54Updated last year
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆95Updated 2 weeks ago
• elliothe / N3H_Core
  [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores
  ☆12Updated 3 years ago
• ACADLab / SPICEPilot
  This repository hosts the information of SPICEPilot: a training free LLM data-augmentation, new bench marking and future road-map.
  ☆19Updated 2 months ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆112Updated last year
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆35Updated 4 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆31Updated last year
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆34Updated 2 years ago
• PeterMonsson / sv_waveterm
  ☆10Updated last year
• mattvenn / fpga-fft
  ☆13Updated 5 years ago
• gicLAB / SECDA
  ☆24Updated 2 years ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆25Updated 7 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆63Updated 6 months ago
• KULeuven-MICAS / htvm
  Efficient Neural Network Deployment on Heterogenous TinyML Platforms
  ☆15Updated last year
• ic-lab-duth / Fast-Float4HLS
  Fast Floating Point Operators for High Level Synthesis
  ☆21Updated 2 years ago