LeiWang1999 / DigitalAlarmClockLinks
njtech digital design. a fpga digital alarm system with Nexys A7 100T
☆54Updated 6 years ago
Alternatives and similar repositories for DigitalAlarmClock
Users that are interested in DigitalAlarmClock are comparing it to the libraries listed below
Sorting:
- 车牌识别,FPGA,2019全国大学生集成电路创新创业大赛☆146Updated 6 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆211Updated 2 years ago
- AXI协议规范中文翻译版☆171Updated 3 years ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆63Updated 7 years ago
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆218Updated 2 months ago
- FPGA实现简单的图像处理算法☆66Updated 2 years ago
- 2023集创赛紫光同创杯一等奖项目☆142Updated 2 years ago
- Step by step tutorial for building CortexM0 SoC☆39Updated 3 years ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛(高云赛道)项目,题目基于高云FPGA的多路网络视频监控编码系统。☆62Updated 2 years ago
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆283Updated 7 years ago
- 帧差法运动目标检测,基于ZYNQ7020☆81Updated 4 years ago
- ☆153Updated last month
- some interesting demos for starters☆93Updated 3 years ago
- ☆228Updated 4 years ago
- AXI总线连接器☆105Updated 5 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆106Updated 4 years ago
- PYNQ学习资料☆174Updated 6 years ago
- CPU Design Based on RISCV ISA☆127Updated last year
- Cortex M0 based SoC☆75Updated 4 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆24Updated 2 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆67Updated 7 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆176Updated 2 years ago
- image processing based FPGA☆115Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆109Updated 7 years ago
- The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…☆45Updated last year
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆121Updated 2 months ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆139Updated 2 years ago
- 【2022集创赛】Arm杯一等奖作品:Cortex-M0智能娱乐收音机 开源项目☆27Updated 2 years ago
- 一个开源的FPGA神经网络加速器。☆184Updated 2 years ago