kennych418 / FPGA_AudioVisualizer
Using an Altera DE10-Lite FPGA development board to simulate an FFT processor. Audio input frequencies will be visualized onto a VGA display.
☆13Updated 4 years ago
Alternatives and similar repositories for FPGA_AudioVisualizer:
Users that are interested in FPGA_AudioVisualizer are comparing it to the libraries listed below
- Verilog Code for I2C Protocol☆17Updated 4 years ago
- Student project for using audio on the DE2-115 FPGA development board.☆27Updated 6 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆95Updated 2 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- A 2D convolution hardware implementation written in Verilog☆44Updated 4 years ago
- Asynchronous fifo in verilog☆33Updated 9 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆14Updated 2 years ago
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆59Updated 3 years ago
- I2C Master Verilog module☆33Updated last month
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆58Updated last year
- UVM and System Verilog Manuals☆41Updated 6 years ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆32Updated 4 years ago
- ☆17Updated 2 weeks ago
- ☆92Updated last year
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- round robin arbiter☆72Updated 10 years ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆22Updated 4 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆55Updated 2 years ago
- An i2c master controller implemented in Verilog☆31Updated 7 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆28Updated 3 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- 10G Low Latency Ethernet☆52Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆75Updated last year
- This project demonstrates DSP capabilities of Terasic DE2-115☆26Updated 6 years ago
- Verilog digital signal processing components☆133Updated 2 years ago
- Simple 8-bit UART realization on Verilog HDL.☆101Updated 11 months ago
- Generate testbench for your verilog module.☆38Updated 7 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 2 years ago