DOOKNET / Digital_Clock
基于FPGA的数字时钟(Modelsim仿真)
☆23Updated 6 years ago
Alternatives and similar repositories for Digital_Clock:
Users that are interested in Digital_Clock are comparing it to the libraries listed below
- Uart transport + image processing + VGA display 基于FPGA的图像处理,包括Uart和VGA☆15Updated 4 years ago
- njtech digital design. a fpga digital alarm system with Nexys A7 100T☆42Updated 5 years ago
- 基于FPGA,VGA,声音传感器与温湿度传感器实现的智能可控数字钟。☆10Updated 4 years ago
- FPGA实现各种小游戏,学习并快乐着☆67Updated 2 years ago
- MP3 Player developed on FPGA(DIGILENT NEXYS 4 DDR)☆19Updated 5 years ago
- riscv指令集,单周期以及五级流水线CPU☆31Updated 3 weeks ago
- 记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU☆11Updated 3 years ago
- 同济大学22级数字逻辑大作业☆30Updated 3 months ago
- FPGA图像处理-- 车牌定位,包括二值化,腐蚀,膨胀,sobel边缘检测,水平投影和垂直投影等☆34Updated last year
- NSCSCC2022龙芯杯个人赛,MIPS32,59MHz经典五级流水线架构,易于初学者阅读(计算机组成原理,自己动手写CPU)☆57Updated 10 months ago
- 单周期 8指令 MIPS32CPU☆89Updated 2 years ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛(高云赛道)项目,题目基于高云FPGA的多路网络视频监控编码系统。☆46Updated last year
- 车牌识别,FPGA,2019全国大学生集成电路创新创业大赛☆131Updated 5 years ago
- 复旦大学 数字逻辑与部件设计实验 2020秋☆45Updated 2 years ago
- 数字IC设计笔试相关的一些电路代码☆9Updated last year
- 同济大学数字逻辑大作业:基于颜色传感器与 OV2640 摄像头的图像处理及显示系统 FPGA camera filter project for 102109 Digital Logic, Fall 2022, Tongji University.☆11Updated 6 months ago
- A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.☆19Updated 8 months ago
- Mips五级流水线CPU☆37Updated 2 years ago
- 电子科技大学,信通学院,综合课程设计,车牌定位识别,附带数据集与训练好的网络☆14Updated 4 years ago
- 同济大学数字逻辑综合作业☆32Updated last year
- 基于verilog的数字时钟,数电课程设计☆32Updated 2 years ago
- 2022年全 国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆31Updated 2 years ago
- 数字逻辑大作业:FPGA的电子琴,基于Nexys 4板,采用Verilog实现☆21Updated 5 years ago
- This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA.☆58Updated 4 years ago
- 提供计算机类,人工智能,深度学习, 计算机视觉, 数字电路, 集成电路设计等各类资料图书的收集☆19Updated 3 years ago
- FPGA的学习路线与书籍整理☆31Updated last year
- 基于Verilog实现的三个MIPS架构CPU项目,按顺序实现了单周期,多周期以及基于多周期的微系统. Three Verilog-based MIPS CPU projects, simulate pipelined cpu based on mips instructi…☆16Updated 3 years ago
- 从零开始设计一个CPU (Verilog)☆50Updated 3 years ago
- The aiming of this project is to realize the image capture using OV5640 camera and FPGA which transmits the image signal using VGA (Video…☆18Updated 4 years ago
- 基于Verilog实现的全数字锁相环☆25Updated 3 years ago