Alternatives and similar repositories for HOG_Zedboard

Users that are interested in HOG_Zedboard are comparing it to the libraries listed below

• mpccelon / hardware-accelerated-hog-svm
  HOG-SVM algorithm implemented in a Zynq 7000 SoC (Digilent ZYBO)
  ☆15Updated 7 years ago
• lp6m / ImageDetectionHW2
  HOG + SVM on FPGA
  ☆26Updated 4 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆46Updated 7 years ago
• mfarhadi / CNNIOT
  ☆46Updated 7 years ago
• markcxli / FPGA_DPU
  This project is to implement YOLO v3 on Xilinx FPGA with DPU
  ☆55Updated 5 years ago
• ilaydayaman / CNN_for_SLR
  A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
  ☆95Updated last year
• sumilao / Zynq-7000-DPU-TRD
  Zynq-7000 DPU TRD
  ☆45Updated 5 years ago
• wutianze / dnndk-pynqz2
  First lesson for you to use DNNDK, also it can be helpful for your AI learning
  ☆71Updated last year
• xupsh / Pynq-CV-OV5640
  Pynq computer vision examples with an OV5640 camera
  ☆47Updated 5 years ago
• medalotte / HLS-canny-edge-detection
  FPGA implementation of Canny edge detection by using Vivado HLS
  ☆51Updated 5 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 4 years ago
• eepro-bt / documents
  文档编写
  ☆13Updated 4 years ago
• cxdzyq1110 / posture_recognition_CNN
  To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different response…
  ☆53Updated 6 years ago
• wbrueckner / cv2pynq
  Python package which accelerates OpenCV image filtering functions for the PYNQ framework
  ☆48Updated 6 years ago
• JinChen-tw / pynqz2_dpu140
  This TRD is implement DPU v1.4.0 on PYNQ-Z2 board
  ☆45Updated 4 years ago
• leonardopennino / PYNQ-Z2-IMPROC
  IMAGE PROCESSING ON XILINX PYNQ Z2 (CANNY, SOBEL)
  ☆26Updated 3 years ago
• phdegen / object_detection_on_zynq_mpsoc
  ☆19Updated 7 years ago
• pp-Innovate / FPGA-ZynqNet
  FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS
  ☆112Updated 7 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 7 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆27Updated 6 years ago
• 2cc2ic / Motion-Detection-System-Based-On-Background-Reconstruction
  This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to buil…
  ☆43Updated 6 years ago
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆110Updated 5 years ago
• 666DZY666 / Design-and-Implementation-of-Face-Recognition-based-on-PYNQ
  Face recognition, computer vision, deep learning, PYNQ, Movidius NCS
  ☆59Updated 6 years ago
• xiangze / CNN_FPGA
  verilog CNN generator for FPGA
  ☆34Updated 4 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆55Updated 5 years ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆67Updated 4 years ago
• h-nasiri / Zynq-Linux-DMA
  DMA enabled Zynq PS-PL communication to implement high throughput data transfer between Linux applications and user IP core.
  ☆39Updated 8 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆105Updated 7 years ago
• 2cc2ic / DMA-S2MM-and-MM2S
  Build an open source, extremely simple DMA.
  ☆22Updated 6 years ago