Implemented Darius IP (originally target PYNQ) of convolution and maxpool on Xilinx FPGA with SDK
☆15Dec 2, 2018Updated 7 years ago
Alternatives and similar repositories for Xilinx-Deep-Learning-Nexys4
Users that are interested in Xilinx-Deep-Learning-Nexys4 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- "智能公交系统电子站牌设计"毕业设计单片机和微信小程序代码☆13Jan 11, 2023Updated 3 years ago
- Implementation of Canny Edge Detection on Cyclone IV. To run project you need Quartus and ModelSim.☆14Mar 29, 2020Updated 5 years ago
- Signal generator designed with Nexy4 FPGA☆13May 14, 2023Updated 2 years ago
- implementation in verilog rtl for an FPGA to detect the presence of a face in an image☆11Mar 12, 2021Updated 5 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆13Mar 30, 2023Updated 2 years ago
- Nexys 4 DDR Artix-7☆11Jun 15, 2018Updated 7 years ago
- In this project, Canny edge detection, one of the efficient edge detection algorithms is implemented on a Zedboard FPGA using verilog. Th…☆23Oct 15, 2021Updated 4 years ago
- CK workflow, portable packages and other artifacts for the ReQuEST-ASPLOS'18 submission:☆12Jan 16, 2019Updated 7 years ago
- FPGA-based Fully Digital FM Transmitter using SDR (Software-Defined Radio) techniquies as up-converter using hpsdm, comb filters, cordic …☆16Mar 15, 2021Updated 5 years ago
- This repository contains the project proposal,code and final report for the implementation of the paper "Parallax Tolerant Image Stitchin…☆14Nov 29, 2018Updated 7 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- ☆10Apr 8, 2021Updated 4 years ago
- ☆12Feb 15, 2024Updated 2 years ago
- 基于FPGA，VGA，声音传感器与温湿度传感器实现的智能可控数字钟。☆10Sep 29, 2020Updated 5 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 2 years ago
- 在FPGA上部署深度学习项目☆24Mar 18, 2021Updated 5 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- ☆11Jan 21, 2019Updated 7 years ago
- C++ HDL (Hardware Description Language)☆45Mar 17, 2026Updated last week
- Modulation and Arbitrary Waveform Generator☆19Feb 16, 2021Updated 5 years ago
- 数字图像处理课程设计，使用Matlab语言编程了一可视化界面，实现对图片的灰度处理，几何操作，代数操作，图像增强，添加噪声，图像退化等功能。比如直方图均衡化，给叶子图像去除叶斑等功能。☆24Mar 5, 2022Updated 4 years ago
- DynamicVINO is an open-source C++ library for establishing easy-to-use, extensible and scalable deep learning inference system for Intel…☆14Aug 21, 2018Updated 7 years ago
- Uart transport + image processing + VGA display 基于FPGA的图像处理，包括Uart和VGA☆18Mar 10, 2020Updated 6 years ago
- 集成电路设计大赛ARM杯作品，获得2021年ARM企业杯☆16Sep 26, 2021Updated 4 years ago
- betrusted.io main SoC design☆14Jan 30, 2020Updated 6 years ago
- Models of finite automata (DFA, NFA) with support of common operations and easily readable creation of objects☆14Feb 4, 2019Updated 7 years ago
- STM32 TDS PH Temperature DS18B20 水质检测☆32May 28, 2018Updated 7 years ago
- This is an HLS-based FPGA accelerator implementation for openpose application.☆14Apr 5, 2019Updated 6 years ago
- Wishbone <-> AXI converters☆13Jun 1, 2015Updated 10 years ago
- Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php☆25Mar 24, 2021Updated 5 years ago
- ☆28Feb 5, 2020Updated 6 years ago
- Simple MIDAS Examples☆12Nov 25, 2018Updated 7 years ago
- Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2☆19Apr 11, 2020Updated 5 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago
- ☆23Oct 7, 2021Updated 4 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- ☆11Jan 21, 2026Updated 2 months ago
- ☆10Mar 3, 2020Updated 6 years ago