Implemented Darius IP (originally target PYNQ) of convolution and maxpool on Xilinx FPGA with SDK
☆16Dec 2, 2018Updated 7 years ago
Alternatives and similar repositories for Xilinx-Deep-Learning-Nexys4
Users that are interested in Xilinx-Deep-Learning-Nexys4 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Design and implementation of a reconfigurable FIR filter in FPGA☆17Sep 26, 2022Updated 4 years ago
- Implementation of Canny Edge Detection on Cyclone IV. To run project you need Quartus and ModelSim.☆15Mar 29, 2020Updated 6 years ago
- Greedy Snake game on Nexys 4 DDR with Verilog.☆31Jul 15, 2022Updated 4 years ago
- Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images☆76Nov 2, 2021Updated 4 years ago
- In this project, Canny edge detection, one of the efficient edge detection algorithms is implemented on a Zedboard FPGA using verilog. Th…☆26Oct 15, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- Nexys 4 DDR Artix-7☆12Jun 15, 2018Updated 8 years ago
- Using verilog-HDL, xilinx-ISE and nexys-iii. A shooting game based on VGA and ps/2 keyboard.☆19Dec 1, 2014Updated 11 years ago
- The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))☆11Sep 27, 2019Updated 7 years ago
- ☆12Feb 15, 2024Updated 2 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车，分为两个部分，控制器部分和小车部分，通过蓝牙信号进行连接。 控制部分可以 通过加速度传感器检测手势，从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆15Mar 10, 2019Updated 7 years ago
- implementation in verilog rtl for an FPGA to detect the presence of a face in an image☆13Mar 12, 2021Updated 5 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 3 years ago
- 在FPGA上部署深度学习项目☆25Mar 18, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- "智能公交系统电子站牌设计"毕业设计单片机和微信小程序代码☆15Jan 11, 2023Updated 3 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- Huffman encoding core (Vivado HLS Project)☆12Oct 15, 2019Updated 6 years ago
- Wishbone to ARM AMBA 4 AXI☆17May 25, 2019Updated 7 years ago
- Companion SmartSpeaker for Senior Citizens with Caregiver Supervision. Runs on a small "headless" device. Preserves privacy but allows …☆16Aug 2, 2026Updated 2 months ago
- e300 and u500 devkits☆10Nov 15, 2020Updated 5 years ago
- An example of on-boarding a PIO block in with duh and wake☆12Nov 18, 2020Updated 5 years ago
- Ethernet MAC for the Digilent Nexys 4 DDR FPGA.☆30Aug 21, 2018Updated 8 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom boa…☆21Jul 9, 2024Updated 2 years ago
- ☆12Feb 16, 2019Updated 7 years ago
- betrusted.io main SoC design☆15Jan 30, 2020Updated 6 years ago
- RADIX-4 SRT division☆13Oct 31, 2019Updated 6 years ago
- Models of finite automata (DFA, NFA) with support of common operations and easily readable creation of objects☆14Feb 4, 2019Updated 7 years ago
- Open source FPGA-based NIC and platform for in-network compute☆18May 22, 2024Updated 2 years ago
- Caffe1 튜토리얼☆13Dec 20, 2017Updated 8 years ago
- This repository contains the project proposal,code and final report for the implementation of the paper "Parallax Tolerant Image Stitchin…☆15Nov 29, 2018Updated 7 years ago
- DynamicVINO is an open-source C++ library for establishing easy-to-use, extensible and scalable deep learning inference system for Intel…☆14Aug 21, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Wishbone <-> AXI converters☆13Jun 1, 2015Updated 11 years ago
- Simple MIDAS Examples☆12Nov 25, 2018Updated 7 years ago
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago
- Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2☆19Apr 11, 2020Updated 6 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- Network components (NIC, Switch) for FireBox☆20Oct 27, 2024Updated last year
- System-on-chip design for NOP in NSCSCC 2023.☆15Aug 21, 2023Updated 3 years ago