yusanshi / Greedy-Snake-VerilogLinks
Greedy Snake game on Nexys 4 DDR with Verilog.
☆30Updated 3 years ago
Alternatives and similar repositories for Greedy-Snake-Verilog
Users that are interested in Greedy-Snake-Verilog are comparing it to the libraries listed below
Sorting:
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9☆33Updated 4 years ago
- 计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集☆18Updated 4 years ago
- 复旦大学 数字逻辑与部件设计实验 2020秋☆54Updated 3 years ago
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆85Updated 6 years ago
- ☆87Updated last month
- 【原创,已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计,FPGA三级存储子系统。☆119Updated 5 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆145Updated last year
- 乱序双发处理器,在2024年计算机系统能力大赛CPU赛道(龙芯杯)获二等奖,全国第四☆15Updated last year
- ☆72Updated 2 years ago
- ☆76Updated 5 years ago
- Vitis 部署加速器工作流介绍☆10Updated 11 months ago
- njtech digital design. a fpga digital alarm system with Nexys A7 100T☆53Updated 6 years ago
- An almost empty chisel project as a starting point for hardware design☆33Updated 10 months ago
- NSCSCC 信息整合☆252Updated 4 years ago
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- ☆63Updated 3 years ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。☆156Updated 6 years ago
- ☆91Updated 2 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆143Updated 7 months ago
- CPU Design Based on RISCV ISA☆126Updated last year
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆20Updated 5 months ago
- A simple RISC-V CPU written in Verilog.☆68Updated last year
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆40Updated 2 years ago
- ☆19Updated 2 years ago
- ☆67Updated last year
- 关于移植模型至gemmini的文档☆32Updated 3 years ago
- 一生一芯的信息发布和内容网站☆134Updated 2 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆66Updated 3 years ago
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆26Updated 3 years ago
- 实现一个基础但功能完善的计算机系统,根据《自己动手写CPU》实现,开发板为Nexys4 DDR☆33Updated last year