Alternatives and similar repositories for Greedy-Snake-Verilog

Users that are interested in Greedy-Snake-Verilog are comparing it to the libraries listed below

• Tan-YiFan / DigitalLogic-Autumn2020
  复旦大学 数字逻辑与部件设计实验 2020秋
  ☆50Updated 3 years ago
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆45Updated 2 years ago
• fluctlight001 / cpu_for_nscscc2020
  2020龙芯杯个人赛 简易双发射60M（含ibuffer）
  ☆35Updated 4 years ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆84Updated 5 years ago
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆58Updated last year
• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆29Updated 3 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆126Updated 4 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆138Updated last year
• spokeyjoe / LoongArchCPU
  A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.
  ☆23Updated last year
• PrimeMHD / FPGA_ThreeLevelStorage
  【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。
  ☆115Updated 5 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆42Updated 4 years ago
• cebarobot / UCAS-Computer-Architecture-Lab
  计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集
  ☆18Updated 3 years ago
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆15Updated 10 months ago
• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆249Updated 4 years ago
• OSCPU / yosys-sta
  ☆73Updated 2 months ago
• LeiWang1999 / DigitalAlarmClock
  njtech digital design. a fpga digital alarm system with Nexys A7 100T
  ☆48Updated 6 years ago
• TCL606 / MipsPipeline
  Mips五级流水线CPU
  ☆41Updated 2 years ago
• iFuProcessor / iFuCore
  ☆19Updated 11 months ago
• qing-2 / CPU
  单周期 8指令 MIPS32CPU
  ☆91Updated 2 years ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆148Updated 6 years ago
• lllbbbyyy / FPGA-OV2640
  This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA.
  ☆55Updated 4 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆68Updated 2 years ago
• Sevenqi7 / NSCSCC-2022
  2022龙芯杯个人赛三等奖作品
  ☆14Updated last year
• USTC-System-Courses / CECS-Lab
  ☆38Updated last year
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 11 months ago
• yufeiran / OpenMIPS
  实现一个基础但功能完善的计算机系统,根据《自己动手写ＣＰＵ》实现，开发板为Nexys4 DDR
  ☆33Updated last year
• OSCPU / ysyxSoC
  ☆86Updated 2 months ago
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆28Updated last year
• MrAMS / NagiCore
  顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel
  ☆22Updated 8 months ago