Alternatives and similar repositories for Greedy-Snake-Verilog:

Users that are interested in Greedy-Snake-Verilog are comparing it to the libraries listed below

• PrimeMHD / FPGA_ThreeLevelStorage
  【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。
  ☆110Updated 4 years ago
• yufeiran / OpenMIPS
  实现一个基础但功能完善的计算机系统,根据《自己动手写ＣＰＵ》实现，开发板为Nexys4 DDR
  ☆33Updated 11 months ago
• LeiWang1999 / DigitalAlarmClock
  njtech digital design. a fpga digital alarm system with Nexys A7 100T
  ☆43Updated 5 years ago
• suisuisi / FPGAandGames
  FPGA实现各种小游戏，学习并快乐着
  ☆67Updated 2 years ago
• Mionger / mp3-player
  MP3 Player developed on FPGA(DIGILENT NEXYS 4 DDR)
  ☆19Updated 6 years ago
• lllbbbyyy / FPGA-OV2640
  This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA.
  ☆58Updated 4 years ago
• likaihz / Greedy_Snake
  数字逻辑课程设计，在Spartan-3的板上实现一个贪吃蛇的小游戏。
  ☆15Updated 9 years ago
• OSCPU / ysyxSoC
  ☆79Updated last week
• yang-le / riscv_cpu
  a simple riscv cpu
  ☆22Updated 2 years ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆36Updated 6 months ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆122Updated 7 months ago
• Tan-YiFan / DigitalLogic-Autumn2020
  复旦大学 数字逻辑与部件设计实验 2020秋
  ☆45Updated 3 years ago
• YutongChenVictor / Fpga-accelerator-demos
  some interesting demos for starters
  ☆69Updated 2 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆57Updated last year
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆77Updated 3 years ago
• OSCPU / yosys-sta
  ☆53Updated last month
• sjj-star / automatically-generate-Wallace-Tree-VerilogHDL-code
  本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。
  ☆23Updated last year
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆25Updated 2 years ago
• peilin-chen / hls_for_cnn_mnist
  【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码
  ☆70Updated 2 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 8 months ago
• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆34Updated last month
• Xinyang-ZHANG / MNIST
  MNIST using tensorflow, c++ and fpga (zynq7010)
  ☆26Updated last year
• 15947470421 / digital_IC_experiment
  我设计了一些数字集成电路的教学实验，供大家学习~
  ☆19Updated 3 weeks ago
• EECS150 / fpga_labs_sp22
  ☆26Updated 2 years ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆72Updated 5 years ago
• ChunxuGuo / SummerSchool2022
  ☆60Updated 2 years ago
• flymin / vgg16-on-Zynq
  Simulating implement of vgg16 network on Zynq-7020 FPGA
  ☆36Updated 5 years ago
• lizhirui / DreamCore
  ☆63Updated 2 years ago
• john9636 / SortingNetwork
  Implement a bitonic sorting network on FPGA
  ☆41Updated 3 years ago
• flymin / LeNet-on-Zynq
  Simulating implement of LeNet network on Zynq-7020 FPGA
  ☆28Updated 5 years ago