Alternatives and similar repositories for Greedy-Snake-Verilog:

Users that are interested in Greedy-Snake-Verilog are comparing it to the libraries listed below

• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆124Updated 8 months ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆72Updated 5 years ago
• LeiWang1999 / DigitalAlarmClock
  njtech digital design. a fpga digital alarm system with Nexys A7 100T
  ☆43Updated 5 years ago
• OSCPU / yosys-sta
  ☆57Updated 2 months ago
• likaihz / Greedy_Snake
  数字逻辑课程设计，在Spartan-3的板上实现一个贪吃蛇的小游戏。
  ☆15Updated 9 years ago
• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆43Updated 2 months ago
• Tan-YiFan / DigitalLogic-Autumn2020
  复旦大学 数字逻辑与部件设计实验 2020秋
  ☆46Updated 3 years ago
• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆26Updated 3 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆42Updated 4 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆59Updated last year
• OSCPU / ysyxSoC
  ☆79Updated last month
• cebarobot / UCAS-Computer-Architecture-Lab
  计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集
  ☆17Updated 3 years ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆22Updated last year
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆39Updated 7 months ago
• RegiaYoung / RISC-V-CPU
  记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU
  ☆12Updated 3 years ago
• BigPig-Bro / udp_gmii_ov5640
  本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛（高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。
  ☆46Updated last year
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆44Updated 2 years ago
• rave1sking / single_cycle_RISCV_CPU_Design-32bit
  Verilog实现单周期非流水线32位RISCV指令集（45条）CPU
  ☆38Updated 4 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 9 months ago
• spokeyjoe / LoongArchCPU
  A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.
  ☆20Updated 9 months ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆19Updated last year
• sjj-star / automatically-generate-Wallace-Tree-VerilogHDL-code
  本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。
  ☆23Updated last year
• suisuisi / FPGAandGames
  FPGA实现各种小游戏，学习并快乐着
  ☆70Updated 2 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆40Updated 4 years ago
• DawnCarol / OpenC910_Modified
  commit rtl and build cosim env
  ☆14Updated last year
• yang-le / riscv_cpu
  a simple riscv cpu
  ☆22Updated 2 years ago
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆48Updated last year
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆62Updated 2 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆43Updated 5 years ago
• yufeiran / OpenMIPS
  实现一个基础但功能完善的计算机系统,根据《自己动手写ＣＰＵ》实现，开发板为Nexys4 DDR
  ☆33Updated last year