Alternatives and similar repositories for Espresso

Users that are interested in Espresso are comparing it to the libraries listed below

• classabbyamp / espresso-logic
  A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.
  ☆145Updated 5 years ago
• genieacs / espresso-iisojs
  Implementation of Espresso-II method for heuristic minimization of single output boolean functions
  ☆29Updated last year
• lsils / kitty
  C++ truth table library
  ☆56Updated 2 weeks ago
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆194Updated last year
• arminbiere / lingeling
  Lingeling SAT Solver
  ☆103Updated last year
• msoeken / cirkit
  A circuit toolkit
  ☆102Updated 5 years ago
• berkeley-abc / abc-zz
  Niklas Een's ABC/ZZ framework
  ☆22Updated 3 years ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆78Updated this week
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆73Updated 4 years ago
• lsils / mockturtle
  C++ logic network library
  ☆232Updated 2 weeks ago
• audemard / glucose
  The glucose SAT solver
  ☆101Updated 7 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆118Updated this week
• aman-goel / avr
  Reads a state transition system and performs property checking
  ☆82Updated 3 months ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆72Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆194Updated 2 months ago
• dreylago / logicmin
  Logic Minimization in Python
  ☆24Updated last year
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆455Updated 3 weeks ago
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆98Updated 3 months ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆22Updated 8 months ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆43Updated last month
• arminbiere / gimsatul
  ☆34Updated 10 months ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆52Updated this week
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆223Updated this week
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆139Updated this week
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆23Updated last year
• dansarie / sboxgates
  Program for finding low gate count implementations of S-boxes.
  ☆40Updated 7 months ago
• uclid-org / uclid
  UCLID5: formal modeling, verification, and synthesis of computational systems
  ☆143Updated 2 months ago
• lsils / bill
  C++ header-only reasoning library
  ☆16Updated 10 months ago
• gatelabdavis / SMTAttack
  SMT Attack
  ☆21Updated 4 years ago
• hadipourh / CryptoHDL
  A list of VHDL codes implementing cryptographic algorithms
  ☆27Updated 3 years ago