Gigantua / Espresso
Espresso heuristic logic minimizer made C++20 Windows 10 compatible - University of California, Berkeley
☆47Updated 11 months ago
Alternatives and similar repositories for Espresso:
Users that are interested in Espresso are comparing it to the libraries listed below
- A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.☆137Updated 4 years ago
- C++ truth table library☆51Updated 10 months ago
- Implementation of Espresso-II method for heuristic minimization of single output boolean functions☆28Updated 11 months ago
- A circuit toolkit☆97Updated 4 years ago
- AIGER And-Inverter-Graph Library☆67Updated last week
- The HW-CBMC and EBMC Model Checkers for Verilog☆65Updated this week
- Showcase examples for EPFL logic synthesis libraries☆192Updated 10 months ago
- Hardware Model Checker☆32Updated this week
- The glucose SAT solver☆92Updated 3 months ago
- C++ logic network library☆221Updated 4 months ago
- CoreIR Symbolic Analyzer☆64Updated 4 years ago
- Reads a state transition system and performs property checking☆76Updated 3 months ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆21Updated last year
- A generic C++ API for SMT solving. It provides abstract classes which can be implemented by different SMT solvers.☆120Updated this week
- An advanced header-only exact synthesis library☆24Updated 2 years ago
- A Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions.☆341Updated 5 months ago
- A tool for synthesizing Verilog programs☆65Updated this week
- Equivalence checking with Yosys☆40Updated last week
- Bitwuzla is a Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, floating-point arithmetic, arrays a…☆238Updated 2 weeks ago
- Pono: A flexible and extensible SMT-based model checker☆91Updated last week
- C++ header-only reasoning library☆13Updated 7 months ago
- Coriolis VLSI EDA Tool (LIP6)☆62Updated last week
- SystemVerilog frontend for Yosys☆74Updated this week
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆21Updated 4 months ago
- C++ parsing library for simple formats used in logic synthesis and formal verification☆35Updated 7 months ago
- ☆34Updated 7 months ago
- Program for finding low gate count implementations of S-boxes.☆39Updated 4 months ago
- A generic parser and tool package for the BTOR2 format.☆41Updated 2 months ago
- Logic Minimization in Python☆23Updated 10 months ago
- Multi-core Decision Diagram (BDD/LDD) implementation☆42Updated last year