tarasap / Microcontroller-4031
☆12Updated last month
Alternatives and similar repositories for Microcontroller-4031:
Users that are interested in Microcontroller-4031 are comparing it to the libraries listed below
- ☆12Updated 6 months ago
- RISC-V Embedded Processor for Approximate Computing☆121Updated 2 months ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 2 weeks ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆13Updated last year
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆221Updated 5 months ago
- This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…☆171Updated 6 months ago
- This repo provide an index of VLSI content creators and their materials☆140Updated 5 months ago
- SystemVerilog Tutorial☆120Updated this week
- Design of a lead-lag controller☆9Updated 11 months ago
- Implementation of RISC-V RV32I☆15Updated 2 years ago
- ☆16Updated last year
- ☆105Updated last year
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆147Updated 4 years ago
- Lecture about FIR filter on an FPGA☆11Updated 8 months ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆53Updated 2 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆32Updated last year
- ☆11Updated last week
- Architectural design of data router in verilog☆28Updated 5 years ago
- ☆130Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆115Updated 3 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆17Updated last year
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- opensource EDA tool flor VLSI design☆31Updated last year
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆13Updated last year
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆13Updated 9 months ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- ☆9Updated 2 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆131Updated this week
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆26Updated 5 years ago