Alternatives and similar repositories for FPGA_pract:

Users that are interested in FPGA_pract are comparing it to the libraries listed below

• miet-mpsu-dsp / labs
  Лабораторные работы по ЦОС (python)
  ☆8Updated 9 months ago
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆58Updated last week
• MPSU / PCU-Verilog-labs
  Методические материалы к лабораторным работам дисциплины "Проектирование цифровых устройств на языке Verilog"
  ☆11Updated last year
• chipdesignschool / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆40Updated last month
• yuri-panchul / basics-graphics-music
  FPGA exercise for beginners
  ☆96Updated this week
• MPSU / MIRISCV
  Открытое RISC-V процессорное ядро MIRISCV для образовательных целей
  ☆12Updated last month
• FPGA-Systems / fpga-awesome-list
  Полезные ресурсы по тематике FPGA / ПЛИС
  ☆158Updated 2 months ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆21Updated 2 months ago
• serge0699 / synth_school_verif_tasks
  Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
  ☆15Updated last month
• nandland / UART
  UART in Verilog and VHDL
  ☆11Updated 2 years ago
• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆35Updated last week
• merldsu / SAP_FPU
  This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.
  ☆18Updated last year
• NickolayTernovoy / risc-v_awesome_list
  ☆48Updated 3 years ago
• nrot / WaveGen
  ☆11Updated last year
• yuri-panchul / yrv-plus
  Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
  ☆25Updated last year
• chipdesignschool / basics-graphics-music
  FPGA exercise for beginners
  ☆34Updated last week
• fpgacademy / DESim
  ☆41Updated 2 months ago
• EvgenyMuryshkin / QuokkaEvaluation
  Example projects for Quokka FPGA toolkit
  ☆37Updated 2 years ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆21Updated 4 years ago
• RomeoMe5 / DDLM
  Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
  ☆54Updated last year
• johan92 / verilog-coding-style
  Verilog (SystemVerilog) coding style
  ☆41Updated 6 years ago
• MIPSfpga / digital-design-lab-manual
  Digital Design Labs
  ☆24Updated 6 years ago
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆70Updated 2 months ago
• iDoka / mastering-fpgasic-book
  Mastering FPGASIC Book
  ☆18Updated 3 years ago
• chili-chips-ba / wireguard-fpga
  Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek sec…
  ☆41Updated this week
• fabriziotappero / opencores-scraper
  few python scripts to clone all IP cores from opencores.org
  ☆19Updated last year
• montedalrymple / yrv
  Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
  ☆17Updated 3 years ago
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated last year
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆51Updated last year
• AngeloJacobo / DDR3-Notes
  My notes for DDR3 SDRAM controller
  ☆28Updated last year