MPSU / FPGA_pract

Related projects: ⓘ

• miet-mpsu-dsp / labs
  Лабораторные работы по ЦОС (python)
  ☆8Updated 4 months ago
• MPSU / PCU-Verilog-labs
  Методические материалы к лабораторным работам дисциплины "Проектирование цифровых устройств на языке Verilog"
  ☆11Updated last year
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆41Updated 3 weeks ago
• nrot / WaveGen
  ☆11Updated last year
• PavlenkoG / ECP5_PCIE_Analyzer
  ☆14Updated 11 months ago
• iDoka / mastering-fpgasic-book
  Mastering FPGASIC Book
  ☆18Updated 2 years ago
• montedalrymple / yrv
  Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
  ☆17Updated 3 years ago
• chili-chips-ba / wireguard-fpga
  Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek sec…
  ☆23Updated last month
• yuri-panchul / basics-graphics-music
  FPGA exercise for beginners
  ☆62Updated this week
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated 10 months ago
• MIPSfpga / digital-design-lab-manual
  Digital Design Labs
  ☆23Updated 5 years ago
• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆30Updated 3 weeks ago
• fabriziotappero / opencores-scraper
  few python scripts to clone all IP cores from opencores.org
  ☆17Updated 8 months ago
• EvgenyMuryshkin / qusoc
  QuSoC demo projects and template
  ☆21Updated 3 months ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆24Updated 2 years ago
• fm4dd / gatemate-riscv
  RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga
  ☆11Updated 10 months ago
• stcmtk / fpga-webinar-2020
  ☆23Updated 4 years ago
• FPGA-InsideOut / hdlgadgets
  human-in-the-loop HDL training tool
  ☆31Updated 6 months ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆53Updated this week
• aignacio / mpsoc_example
  ☆56Updated 3 years ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆18Updated 6 months ago
• iDoka / eda-scripts
  Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
  ☆28Updated 2 months ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆33Updated 3 years ago
• ChinaQMTECH / ZYNQ_BAJIE_BOARD
  ☆19Updated last year
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆54Updated this week
• EvgenyMuryshkin / QuokkaEvaluation
  Example projects for Quokka FPGA toolkit
  ☆36Updated last year
• marsohod4you / Amber-Marsohod2
  Port of Amber ARM Core project to Marsohod2 platform
  ☆12Updated 4 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆32Updated 5 years ago
• umarcor / hwstudio
  GUI editor for hardware description designs
  ☆26Updated last year
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆20Updated 3 years ago